Sun Microsystems, Inc.

Hong Hao

Kanti Bhabuthmal

Richard F Avra

Ramachandra P Kunda

James C Hunt

Saied Bozorgui-Nesbat

A clock generation and control circuit to debug an integrated circuit includes a multiplexer connected to a set of input lines that carry a set of clock signals. The multiplexer selects one of the input lines in response to a select signal generated by a decode circuit. A control circuit provides input signals to the decode circuit. The control circuit specifies a disabled output clock signal in response to a stop signal applied to a single external pin of the integrated circuit. Alternately, the control circuit specifies a disabled output clock signal through a test access port of the integrated circuit. Debug operations are executed while the output clock signal is disabled.

Method and apparatus for fully controllable integrated circuit internal

A method for identifying false paths in a digital circuit. A list of paths corresponding to the digital circuit is either provided or generated. For each path, an AND gate is created. For each element in the path, the off-path signals of the monitor circuits corresponding to the elements of the path are coupled to the input of the AND gate. A plurality of different signals are input to the digital circuit in an attempt to generate a '1' at the output of the AND gate. A false timing path signal is generated for that path if the AND gate does not output a '1' within a pre-determined amount of time. This process is repeated for each path of the digital circuit to identify all false timing paths.

Apparatus and method identifying false timing paths in digital circuits

A method is disclosed for loading a compiled test program into a microprocessor's internal caches and then controlling the execution of that program. Initially, the microprocessor's internal clock is disabled. Then for each memory location specified in the compiled program, the memory content associated with that location is loaded into the appropriate microprocessor cache. This is accomplished in two primary steps. First, the memory content is shifted into positions on the pins of the microprocessor by a boundary scan shift operation via an IEEE 1149.1 interface. Second, after the pins have the appropriate bit values for the current memory content, an external clock supplies the microprocessor with clock cycles that are then used by the microprocessor to control the loading of data/instructions from the pins into the appropriate data or instruction cache. The process of loading the pins with data via boundary scan, and then shifting the data into appropriate caches is repeated for each memory content of the compiled program until all instructions in the program have been loaded into the appropriate caches. Thereafter, the microprocessor is forced into normal execution mode by resetting the microprocessor to reenable its internal clock. Finally, the test program is executed in a manner that allows a user to interact with the microprocessor during execution.

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Sunnyvale, CA, United States of America

Hong Hao