Realtek Semiconductor Inc.

Hong-Hai Dai

Dong-Yu He

Li-Cong Hou

Yang Li

Qing-Zhe Qiu

Shao-Hua Jin

Jiayuan Tan

Hai-Tao Li

A die package structure and a method for fabricating the same are provided. The method includes: fixing a first die on a package base; aligning first hollow pads of a flexible printed circuit board with first pads of the first die, and fixing the flexible printed circuit board; soldering the first hollow pads to the first pads; fixing a second die on the flexible printed circuit board to overlap with the first die; folding the flexible printed circuit board, such that second hollow pads of the flexible printed circuit board are aligned with second pads of the second die, and signal test pads of the flexible printed circuit board are exposed; fixing the flexible printed circuit board on the second die; soldering the second hollow pads to the second pads; soldering metal wires to the signal test soldering pads; and soldering package pins to the metal wires.

Die package structure and method for fabricating the same

A method for authentication data transmission and a system thereof are provided. The method is operated in a computer system that is connected to a biometric device, and a secure channel is established there-between according to a security protocol. The computer system can receive encrypted biometric feature data from the biometric device based on a request. In a secure environment built in the computer system, the biometric feature data is decrypted and biometric features can be extracted. A comparison result is generated after comparing the biometric features with feature data in a database. The comparison result can be transmitted to the biometric device. The comparison result is then encrypted in the biometric device according to the security protocol. The biometric device can therefore transmit the encrypted comparison result to the computer system via the secure channel.

Method and system for authentication data transmission

The present disclosure discloses a multi-path image processing apparatus. An image merging circuit is configured to receive image frames that at least one of the image frames has a largest row number, generate redundant pixel row for each of the image frames that has a row number smaller than the largest row number such that the row number of each of the image frames equals to the largest row number, generate redundant pixel columns for each of the image frames having the number thereof determined by a size of a largest operation window, and merge each two of the image frames through the redundant columns thereof to generate a merged image frame. An image processing circuit performs image processing procedure on the merged image frame to generate a processed merged image frame, wherein at least a part of the image processing procedure is operated according to the largest operation window. An image segmentation circuit segments the processed merged image frame to generate processed image frames.

Multi-path image processing apparatus and method

A saturation adjusting apparatus for processing a pixel, which has three color components each having a value falling within a range defined by upper and lower extreme values, of a RGB color model includes an extreme value controller and a component adjuster. The extreme value controller determines maximum and minimum extreme value thresholds for ensuring that the values of the color components of the pixel after undergoing linear color correction processing based on a correction indicator fall within the range defined by the upper and lower extreme values. The component adjuster includes a decision-making unit for choosing the correction indicator from a group of values which includes the maximum extreme value threshold, the minimum extreme value threshold, and a saturation setting. The component adjuster further includes a color corrector for performing linear color correction processing on the three color components of the pixel using the correction indicator.

Saturation adjusting apparatus and method thereof

An edge detection apparatus includes a computing circuit and a determining circuit. The computing circuit includes a first multiplier block and a first adder unit. The first multiplier block includes n&#xd7;m first multiplier units, wherein each first multiplier unit has a first multiplication factor. The n&#xd7;m first multiplier units respectively perform multiplications on n&#xd7;m pixels which are arranged as an n&#xd7;m matrix to generate n&#xd7;m first product values based on the corresponding first multiplication factors. The n&#xd7;m pixels include a target pixel, where n is not equal to m. The first adder unit generates a first computation result according to the n&#xd7;m first product values. The determining circuit determines if the target pixel is an edge pixel according to at least the first computation result.

Growing community of inventors

Suzhou, China

Hong-Hai Dai