Skhynix Inc.

Hong Gyeom Kim

Min Su Park

Jong Chern Lee

Heat Bit Park

Byung Kuk Yoon

Min Sik Han

Dae Ho Ra

A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.

Semiconductor device

A data alignment device includes a buffer configured to buffer a data strobe signal, output a data strobe pulse signal, and buffer inputted data, a latch configured to latch the data in correspondence to the data strobe pulse signal, a first delay configured to delay the data strobe pulse signal and output a delayed signal, a divider configured to divide the delayed signal at a time of activation of a division control signal and generate a plurality of divided signals, a control circuit configured to receive a command signal, a clock, the data strobe signal, and the plurality of divided signals, and control the division control signal for controlling an enable state of the divider, and an alignment circuit configured to align output data in correspondence to the plurality of divided signals.

Data alignment device

A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.

Semiconductor apparatus having through via capable of testing connectivity of through via

A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an I/O driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.

Semiconductor apparatus

Various embodiments of a fuse circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the fuse circuit may include a fuse whose electrical connection state can be changed by an electrical stress applied thereto and a plurality of self boosting units configured to perform self boosting operations under the control of a rupture enable signal. The self boosting units may also be configured to generate stress voltages and supply the generated stress voltages to the fuse. The fuse circuit may also include a precharge unit configured to supply a precharge voltage to the fuse in response to a precharge signal and a cross-coupled latching amplification unit configured to sense a change in a voltage level of the precharge voltage supplied to the fuse, with reference to a reference voltage, and output a fuse state signal.

Growing community of inventors

Icheon-si, South Korea

Hong Gyeom Kim