Fuji Electric Co., Ltd.

Fuji Electric Systems Co. Ltd.

Hong-fei Lu

Haruo Nakazawa

Toru Muramatsu

Akio Sugi

Shinichi Jimbo

Tatsuji Nagaoka

Mizushima Tomonori

IGBT includes an n-type drift layer, an n-type accumulation layer provided on the upper surface of the drift layer having higher impurity concentration than the drift layer, a base layer provided on the upper surface of the accumulation layer, a gate electrode embedded inside a striped gate trench penetrating the base layer and the storage layer through a gate insulating film, and a dummy electrode embedded inside a dummy trench provided to face the gate trench across the base layer and the accumulation layer through a dummy insulating film. The base layer has a p-type active base region and a p-type floating base region arranged alternately in the extending direction of the gate trench, and an n-type base isolation region isolating the active base region and the floating base region.

Insulated gate bipolar transistor

A power conversion apparatus includes N semiconductor modules respectively including a switch part including first and second semiconductor switches coupled in series, and an output terminal coupled to a node that connects the first and second semiconductor switches, where N is an integer greater than or equal to 3, wherein the N semiconductor modules are arranged so that the output terminals thereof are adjacent to each other. The power conversion apparatus further includes an output bar to couple the output terminals of the N semiconductor modules so that a parasitic inductance of a current path coupling the output terminals of first and second semiconductor modules among the N semiconductor modules, and a parasitic inductance of a current path coupling the output terminals of the first and third semiconductor modules among the N semiconductor modules, are approximately balanced.

Power conversion apparatus having semiconductor modules each including series-connected semiconductor switches and output terminal coupled to node connecting semiconductor switches, and output bar coupling output terminals of semiconductor modules

A semiconductor device is provided, the semiconductor device including a base layer of a first conductivity type having a MOS gate structure formed on a front surface side thereof, a collector layer of a second conductivity type formed on a rear surface side of the base layer, and into which a first dopant and a second dopant which is different from the first dopant are implanted, and a collector electrode formed on a rear surface side of the collector layer, wherein an impurity concentration peak of the second dopant is at a deeper position from the rear surface of the collector layer than an impurity concentration peak of the first dopant, and magnitude of the impurity concentration peak of the second dopant is larger than 1/100 of magnitude of the impurity concentration peak of the first dopant.

Semiconductor device and method of manufacturing semiconductor device

An RB-IGBT is provided that has a new emitter trench structure with improved breakdown voltage achieved by improving the electrical field distribution of the drift region. The RB-IGBT includes an isolation region having a first conductivity type on a side surface of a semiconductor substrate. The semiconductor substrate includes a drift region having a second conductivity type; a collector region having the first conductivity type and provided farther downward than the drift region; and an emitter trench portion provided extending to the drift region in a thickness direction from a front surface to a back surface of the semiconductor substrate. The emitter trench portion includes a trench electrode electrically connected to an emitter electrode provided above the semiconductor substrate; an upper trench insulating film directly contacting a bottom portion and side portions of the trench electrode; and a lower trench insulating film provided below the upper trench insulating film.

RB-IGBT

An n-type low lifetime adjustment region is provided in a portion inside an ntype drift region deeper than the bottom surface of a termination p-type base region or p-type guard ring from a substrate front surface, separated from the termination p-type base region and the p-type guard ring. The carrier lifetime of the n-type low lifetime adjustment region is shorter than the carrier lifetime of the ntype drift region. Because of this, it is possible to provide a reverse blocking IGBT such that it is possible to suppress both a high temperature reverse leakage current and an increase in turn-off loss, while suppressing deterioration in the trade-off relationship between the turn-off loss and the on-state voltage.

Semiconductor device and semiconductor device manufacturing method

A semiconductor device including: a first conductivity type n-type drift layer; a second conductivity type VLD region which is formed on a chip inner circumferential side of a termination structure region provided on one principal surface of the n-type drift layer and which is higher in concentration than the n-type drift layer; a second conductivity type first clip layer which is formed on a chip outer circumferential side of the VLD region so as to be separated from the VLD region and which is higher in concentration than the n-type drift layer; and a first conductivity type channel stopper layer which is formed on a chip outer circumferential side of the first clip layer so as to be separated from the first clip layer and which is higher in concentration than the n-type drift layer. Thus, it is possible to provide a semiconductor device having a stable and high breakdown voltage termination structure in which the length of a termination structure region is small as well as the immunity to the influence of external charge is high.

Semiconductor device

A semiconductor device manufacturing method for a semiconductor device having a p-n junction formed of a first conductivity type first semiconductor region and a second conductivity type second semiconductor region, and comprising a low-lifetime region that has a carrier lifetime shorter than that in other regions at the interface of the p-n junction. The method includes an implantation process of, after implanting a second conductivity type impurity into the surface of the first semiconductor region with a first acceleration energy, implanting a second conductivity type impurity, with a second acceleration energy differing from the first acceleration energy, into the surface of the first semiconductor region into which the second conductivity type impurity has been implanted.

Semiconductor device manufacturing method

A semiconductor device having a p+ collector region in the surface of an n&#x2212; drift region. The p+ collector region forms a p-n junction with the n&#x2212; drift region. A collector electrode is in contact with the p+ collector region. A low-lifetime region having a carrier lifetime shorter than in other regions is provided, extending from the n&#x2212; drift region to the p+ collector region, at the interface between the n&#x2212; drift region and p+ collector region. The low-lifetime region, being partially activated in accordance with the concentration distribution of a p-type impurity implanted in order to form the p+ collector region, is in a barely activated state. The low-lifetime region has an activation rate lower than that of the p+ collector region. The p+ collector region is completely electrically activated as far as a depth of, for example, 0.5 &#x3bc;m-0.8 &#x3bc;m, from the surface on the collector electrode side.

Semiconductor device with low-lifetime region

An A-NPC circuit is configured so that the intermediate potential of two connected IGBTs is clamped by a bidirectional switch including two RB-IGBTs. Control is applied to the turn-on di/dt of the IGBTs during the reverse recovery of the RB-IGBTs. The carrier life time of an ndrift region in each RB-IGBT constituting the bidirectional switch is comparatively longer than that in a typical NPT structure device. A low life time region is also provided in the interface between the ndrift region and a p collector region, and extends between the ndrift region and the p collector region. Thus, it is possible to provide a low-loss semiconductor device, a method for manufacturing the semiconductor device and a method for controlling the semiconductor device, in which the reverse recovery loss is reduced while the reverse recovery current peak and the jump voltage peak during reverse recovery are suppressed.

Semiconductor device, method for manufacturing the semiconductor device, and method for controlling the semiconductor device

Plural island-form emitter cells () having a p-base region () and an nemitter region () are provided, distanced from each other, on a main surface of an nlayer (). A trench () deeper than the p-base region () is formed on either side of the emitter cell (). A first gate electrode () is embedded in the trench () across a first gate insulating film (). A second gate electrode () that electrically connects first gate electrodes () is provided, across a second gate insulating film (), on a surface of a region of the p-base region () sandwiched by the nemitter region (). A conductive region () that electrically connects second gate electrodes () is provided, across a third gate insulating film (), on a surface of the nlayer (). A contact region () that is isolated from the second gate electrode (), and that short circuits the nemitter region () and p-base region (), is provided.

Aspects of the invention are related to a semiconductor device including a first conductivity type n-type drift layer, a second conductivity type VLD region which is formed on a chip inner circumferential side of a termination structure region provided on one principal surface of the n-type drift layer and which is higher in concentration than the n-type drift layer, and a second conductivity type first clip layer which is formed on a chip outer circumferential side of the VLD region so as to be separated from the VLD region and which is higher in concentration than the n-type drift layer. The invention can also include a first conductivity type channel stopper layer which is formed on a chip outer circumferential side of the first clip layer so as to be separated from the first clip layer and which is higher in concentration than the n-type drift layer.

Mirror-polished CZ wafer and FZ wafer are prepared. A first impurity region which will be a first isolation region is formed in a surface layer of a first main surface of the CZ wafer. The first main surface of the CZ wafer and a first main surface of the FZ wafer are bonded to each other by an inter-molecular bond. A second impurity region which will be a second isolation region is formed in a surface layer of a second main surface of the FZ wafer. A heat treatment is performed to diffuse the first impurity region and the second impurity region such that the first impurity region and the second impurity region are continuous, thereby forming a through silicon isolation region.

Method of manufacturing semiconductor device

A lateral high-breakdown voltage semiconductor device is provided in which the breakdown voltages of elements as a whole are improved, while suppressing increases in cell area. A track-shape gate electrode surrounds a collector electrode extending in a straight line, a track-shape emitter electrode surrounds the gate electrode, and a track-shape first isolation trench surrounds the emitter electrode. A second isolation trench surrounds the first isolation trench. The region between the first isolation trench and the second isolation trench is an n-type isolation silicon region. The isolation silicon region is at the same potential as the emitter electrode. In the cross-sectional configuration traversing the gate electrode, the depth of the p base region in an interval corresponding to an arc-shape portion of the gate electrode is shallower than the depth of the p base region in an interval corresponding to a straight-line portion of the gate electrode.

Growing community of inventors

Matsumoto, Japan

Hong-fei Lu