Industrial Technology Research Institute

Hong-Chich Chou

Jerng-Cherng Fan

Won-Yih Lin

Ching-Chin Huang

Po-Chuan Kang

Tsahn-Yih Chang

An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one destination processor associated therewith for servicing the interrupt request. An interrupt controller in accordance with the present invention applies latched interrupt requests to a priority compare tree which serves to prioritize received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. Similar determinations are made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt. The destination selection circuit attempts to determine a unique destination processor for each of the highest priority interrupt requests, such that these multiple interrupt requests can therefore be dispatched to different processors simultaneously. One or more of the interrupt requests may be 'blocked' during a particular time period because all destination processors which could service the blocked requests are already processing other interrupts, performing higher priority tasks or are otherwise unavailable. These blocked interrupt requests are identified and the corresponding destination registers are masked such that the remaining non-blocked interrupt requests can be delivered to an available destination processor.

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Hsinchu, Taiwan

Hong-Chich Chou