Intel Corporation

Hong Bin Liao

Subramaniam M Maiyuran

Guei-Yuan Lueh

Supratim Pal

Abhishek R Appu

Joydeep Ray

Altug Koker

Prasoonkumar Surti

Travis T Schluessler

Varghese George

Ankur N Shah

David M Puffer

Devan Burke

Jonathan Kennedy

Jorge E Parra

Stephen Junkins

Chandra S Gurram

Ashutosh Garg

Shubra Marwaha

Timothy R Bauer

Shubh Shah

Konrad Trifunovic

Weiyu Chen

Gang Y Chen

Junjie Gu

Joy Chandra

Ananda V Kommaraju

Mike MacPherson

Mike B Macpherson

Gang Chen

Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes systolic dot product circuitry to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

Instruction and logic for systolic dot product with accumulate

An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

Control flow mechanism for execution of graphics processor instructions using active channel packing

Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

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Beijing, China

Hong Bin Liao