Mosaid Technologies Corporation

Conversant Intellectual Property Management Incorporated

Novachips Canada Inc.

Other

Mosaid Technologies Incorproated

Hong Beom Pyeon

Jin-Ki Kim

HakJune Oh

Shuji Sumi

Peter B Gillingham

Bruce Millar

Steven Przybylski

Peter Vlasenko

Roland Schuetz

Young-Goan Kim

Kin-Ki Kim

Hunsam Jung

Hakjune Oh

Steven A Przybylski

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Non-volatile memory device with concurrent bank operations

Non-volatile memory device

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Method and system for accessing a flash memory device

A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

Bridging device having a configurable virtual page size

Memory with output control

Flash memory device

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

System and method of page buffer operation for memory devices

Flash memory system

An apparatus comprising a plurality of devices connected in series with one another, each of the devices comprising a test enable pin for receiving a test enable signal that indicates enablement of a test mode, and a test output pin for outputting a test output signal in the test mode, and a controller coupled to the devices and comprising an additional test output pin for outputting a test channel output signal, wherein a failure of at least one of the test output signals and the test channel output signal indicates the existence of one or more potential defects associated with the plurality of devices and the controller.

Method and apparatus for testing surface mounted devices

Growing community of inventors

Kanata, Canada

Hong Beom Pyeon