Samsung Electronics Co., Ltd.

Hong-Beom Kim

Sung-Hwan In

Sang-Seok Kang

Hyun-Soon Jang

Young-Tae Kim

Min-Su Jung

Sang-Hyeon Kim

Sang-seok Kang

Yong-Jin Park

Ho-Jin Park

Hee-Jun Lee

Boo-Jin Kim

Byung-Heon Kwak

Il-Sung Jeong

Kyu-Young Nam

Ha-Il Kim

A board assembly includes: a circuit board; a shield member coupled to the circuit board to face the circuit board; and at least one socket for a storage medium which is mounted on the circuit board. The shield member includes an opening that exposes the entirety of the socket to the outside. The board assembly forms an opening in a dual recess structure to accommodate the socket. Thus, the board assembly may contribute to the reduction of the thickness of an electronic device while being stacked with a battery. Further, the entire socket is exposed to the outside of the shield member, the storage medium may be easily removed.

Board assembly

A method of testing a semiconductor memory device includes writing first data to a memory cell array in the semiconductor memory device, loading second data from the memory cell array onto a plurality of data pads of the semiconductor memory device, rewriting the second data to the memory cell array, and outputting test result data through one or more test pads. The first data is received from an external device through the one or more test pads, which correspond to one or more of the plurality of data pads. The test result data is based on the rewritten data in the memory cell array.

Method of testing a semiconductor memory device

A memory device includes a memory cell array to store data, a register to store test data, and a decision circuit to invert the test data and to determine a failure of at least one memory cell within the memory cell array responsive to the data, the test data, and the inverted test data.

Parallel bit testing device and method

A semiconductor memory device according to embodiments of the invention includes N channels for interface with an outside. During a test mode where the semiconductor memory device is tested by a tester having M channels, K ones of the N channels of the memory device are connected to the M channels of the tester, N being more than M and M being equal to or more than R*K (where R is an integer).

Semiconductor memory device capable of accessing all memory cells

A semiconductor memory device comprises: a write data controller for receiving predetermined bits of data inputted through data input/output pins to generate plural bits of data, and a read data controller for serially converting the plural bits of data to generate serially converted data through one of the data input/output pins during a test operation; and the write data controller for receiving plural bits of data inputted through the input/output pins to generate the plural bits of data, and the read data controller for receiving the plural bits of data to generate the plural bits of data through the data input/output pins during a regular operation, wherein the number of the plural bits is N times the number of the predetermined bits. N being a natural number.

Semiconductor memory device and test method of the same

A semiconductor chip test system and test method thereof are provided. The system having a plurality of data input/output pins, a tester for inputting/outputting data through the plurality of data input/output pins; a plurality of semiconductor chips to be tested by the tester; a control circuit for sequentially outputting the output data from each of the plurality of semiconductor chips to the tester during a read operation and simultaneously supplying the input data from the tester to the semiconductor chips during a write operation.

Apparatus and method for testing a plurality of semiconductor chips

The present invention relates to a fuse option circuit of an integrated circuit and a method thereof. More particularly it concerns a fuse option circuit comprising: a first fuse formed on a chip, which is cut by providing a larger electric current than a set value; a second fuse formed on the chip identically with the first fuse; a fuse cutting means providing a cutting current loop to the first fuse in response to a fuse cutting signal; and an option signal generating means which produces a fuse option signal by comparing resistance values of the first and second fuses. Accordingly, even if the first use is abnormally cut, the fuse option can be precisely provided by comparing the first fuse having a changed resistance after cutting process with the second fuse keeping an initial resistance value. Therefore, the reliability of a fuse option of an integrated circuit can be improved.

Fuse option circuit of integrated circuit and method thereof

A voltage clamping circuit for a semiconductor memory device which is capable of rapidly coping with the demand of the user. The voltage clamping circuit includes PMOS transistors connected in series between an external supply voltage terminal and a node on an output line of a DC voltage generator, a control PMOS transistor having a channel connected at both ends thereof respectively to the node on the output line and a node between the second and third ones of the series-connected PMOS transistors, and a pad connected to a control electrode of the control PMOS transistor. The pad is selectively connected to a supply voltage in a first state and to a ground voltage in a second state, thereby controlling a clamping interval of the clamping means to be variable. The first state is a state requiring a longer clamping interval than that of the second state.

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Suwon, South Korea

Hong-Beom Kim