Samsung Electronics Co., Ltd.

Hong-bae Park

Yu-Gyun Shin

Sang-Jin Hyun

Sug-Hun Hong

Jin-wook Lee

Hyung-seok Hong

Hag-ju Cho

Hye-Lan Lee

Hoon-joo Na

Myeong-Cheol Kim

Sang-Bom Kang

Ja-hum Ku

Kyoung-Seok Kim

Hyung-Seok Hong

Sung-kee Han

Byung-Hee Kim

Hoon-Joo Na

Jae-Jong Han

Kye-Hyun Baek

Min-chan Gwak

Byung-Ho Ahn

Seung Mok Shin

Chang-yeon Lee

Hwa-Sik Kim

Young-sun Kim

Sung-Tae Kim

Ki-chul Kim

Jung-Hyun Lee

Young-wook Park

Cha-young Yoo

Dong-Soo Lee

Chang-seok Kang

Jae-Soon Lim

Cha-Young Yoo

Beom-jun Jin

Gab-Jin Nam

Taek-Soo Jeon

Bong-hyun Kim

Hag-Ju Cho

Seong-Geon Park

Sug-hun Hong

Jae-Yeol Song

Jae-Hyun Lee

Sang-jin Hyun

Doo-sup Hwang

Jong-Han Lee

June-hee Lee

Jong-wan Kwon

Hye-Ian Lee

Hoon-ju Na

Hoon-joo Nah

Min-Seok Jo

An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

Method of manufacturing an integrated circuit device including a fin-type active region

A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.

Semiconductor device

Integrated circuit device including an overhanging hard mask layer

A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

Integrated circuit device and method of manufacturing the same

Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.

CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device

A semiconductor device includes a fin-type active region; a gate dielectric layer covering an upper surface and opposite lateral surfaces of the fin-type active region; and a gate line extending on the gate dielectric layer to cover the upper surface and opposite lateral surfaces of the fin-type active region and to cross the fin-type active region. The gate line includes an aluminum (Al) doped metal-containing layer extending to cover the upper surface and opposite lateral surfaces of the fin-type active region to a uniform thickness, and a gap-fill metal layer extending on the Al doped metal-containing layer over the fin-type active region. Related fabrication methods are also described.

Fin-type field effect transistors including aluminum doped metal-containing layer

A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

Method of fabricating semiconductor device having dual gate

A complementary metal oxide semiconductor (CMOS) device including: a semiconductor substrate including a NMOS region and a PMOS region; a NMOS metal gate stack structure on the NMOS region and including a first high dielectric layer, a first barrier metal gate on the first high dielectric layer and including a metal oxide nitride layer, and a first metal gate on the first barrier metal gate; and a PMOS metal gate stack structure on the PMOS region and including a second high dielectric layer, a second barrier metal gate on the second high dielectric layer and including a metal oxide nitride layer, and a second metal gate on the second barrier metal gate.

Complementary metal oxide semiconductor device having metal gate stack structure and method of manufacturing the same

The method involves providing a semiconductor substrate comprising first and second regions in which different conductive metal-oxide semiconductor (MOS) transistors are to be formed. A gate dielectric layer above the semiconductor substrate sequentially forming a first metallic conductive layer and a second metallic conductive layer on and above the gate dielectric layer; covering the second region with a mask, and performing ion plantation of a first material into the first metallic conductive layer of the first region. Removing the second metallic conductive layer of the first region and forming a first gate electrode of the first region and a second gate electrode of the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region. The first and second regions of the semiconductor substrate having different work functions because the gate electrodes of the first and second regions have different thicknesses and at least one of the first and second gate electrodes include impurities.

Method of manufacturing dual gate semiconductor device

A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer.

Methods of forming semiconductor devices having gates with different work functions using selective injection of diffusion inhibiting materials

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Seoul, South Korea

Hong-bae Park