Adaptec, Inc.

Stmicroelectronics Gmbh

Honda Yang

John T Gill, Iii

Bruce Pember

Thomas Kennith Geiger

Christine Odero

The interconnect pin count between field programmable gate arrays (FPGAS) used in prototyping an application specific integrated circuit (ASIC) is reduced without compromising the prototyping by using serial links between the FPGAs. A block A of the ASIC is programmed in a first FPGA. A block B of the ASIC is programmed in a second FPGA. Blocks A and B are identical between ASIC and FPGA implementations. Block A communicates with block B via two interconnected wrappers, which are, in this example, serial COM wrappers connected by a serial link.

Programmable logic device partitioning method for application specific integrated circuit prototyping

An iterative method and system are disclosed for locating errors in interleaved code words. The system and method generate column parity check symbols using symbols from selected columns in the interleaved code words. The width of each column parity check symbol is reduced, followed by the reduced column parity check symbols being merged to create merged column check symbols. A Reed-Solomon encoding algorithm is performed on the merged column check symbols to generate error locating check symbols which are combined with the reduced column parity check symbols to create an error locating code word. The error locating check symbols are stored with the interleaved code words in memory. Following retrieval from memory, the error locating code word is reconstructed and decoded upon the detection of at least one uncorrectable interleaved code word from decoding the interleaved code words. Errors identified from decoding the error locating code word are marked as erasures in the appropriate columns of the interleaved code words. Decoding of the previously uncorrectable interleaved code words is subsequently performed.

Redundancy system and method for locating errors in interleaved code words

A system and method are disclosed for providing error correction coding having a selectively variable degree of redundancy. The system and method include generating extended check symbols by performing a Reed-Solomon operation on unused check symbols that do not form a portion of an interleaved code word. An extended check symbol is generated from the unused check symbols appearing in a column of the unused check symbols. The extended check symbols are stored with the interleaved code words in a data storage device. The extended check symbols are retrieved from the data storage device with the corresponding interleaved code words. Following the decoding of the interleaved code words and the identification of uncorrectable errors therein, the extended check symbols are decoded to recover the corresponding unused check symbols for the previously uncorrectable interleaved code words. The recovered unused check symbols are added to the previously uncorrectable interleaved code words so as to increase the error correcting capability thereof. The previously uncorrectable interleaved code words having the recovered unused check symbols are then decoded and errors therein corrected accordingly.

System and method for providing error correction coding with selectively variable redundancy

Disclosed is a thermal asperity pointer processing apparatus and method for processing apparatus for generating erasure locations from a thermal asperity signal. The thermal asperity signal indicates an error burst in an interleaved data sector. The apparatus includes a thermal asperity pointer recorder, a storage unit, and a thermal asperity pointer processing unit. The thermal asperity pointer recorder is adapted to receive a thermal asperity signal and is configured to generate a thermal asperity event information associated with the thermal asperity signal. The thermal asperity event information includes a thermal asperity duration, a starting interleave number, and a starting interleave address of the thermal asperity signal in the interleaved data sector. The storage unit is configured to receive the thermal asperity event information from the thermal asperity pointer recorder and is configured to store the thermal asperity duration, starting interleave number, and starting interleave address associated with the thermal asperity signal. The thermal asperity pointer processing unit is coupled to receive the thermal asperity event information from the storage unit and is adapted to generate the erasure locations for interleaves corresponding to the error burst in the data sector.

Apparatus and method for generating interleave erasure locations from thermal asperity erasure pointers

Disclosed are methods and computer readable media containing program instructions for testing alternating current characteristics of a computer model of an integrated circuit design. The testing implements an associated AVF file and an associated DUT file for the integrated circuit design. The computer readable media includes: (a) program instructions for generating a test file containing data of a parameter of the integrated circuit design, the test file being generated based upon whether a pair of signals are either both inputs, or one is an input and another is an output; (b) program instructions for parsing through a chip file of the integrated circuit design in order to extract netlist information, external signal names, bus definitions, and pull-up information; (c) program instructions for parsing through the DUT file to extract input/output information, channel number information, and timing information; (d) program instructions for splitting data of the AVF file into input vector data and output vector data; (e) program instructions for generating an environment file that assists in simulating a physical test station; and (f) program instructions for running the environment file using the input vector data and the output vector data in order to generate a log that indicates alternating current test results for the parameter data.

Automated alternating current characterization testing

Disclosed is a method for generating AVF test file data for use in testing a simulation of an integrated circuit design, and verifying the generated AVF test file data before they are delivered to a physical silicon version of the integrated circuit design. The generation method includes providing a map file that contains a plurality of identifying statements for each multiple port I/O cell (or also including single port I/O cells) in the integrated circuit design. Then, generate a verilog executable file for the integrated circuit design. The verilog executable file is configured to contain data associated with the map file, a netlist of the integrated circuit design, output enable data derived from the netlist, and AVF data conversion information. The method further comprises executing the verilog executable file along with a test bench that includes the netlist of the integrated circuit design, a set of test files, and models. The execution is configured to produce the AVF test file data and a DUT timing file data. The generated data is then processed through a verification loop that is configured to identify in a log all of the possible errors with the generated test data. The input data used to generate the AVF test file data may then be modified to enable the re-generation of new AVF test file data and new DUT timing file data. If errors are still present, the loop may again be re-run, if the errors are of the kind that would necessitate correction. Once the verification loop has been run to the satisfaction of the test engineer, the test vector data can be applied to the physical test station for use on the physical silicon chip.

Automated test vector generation and verification

Disclosed is an error detection and correction device for extending error correction time on a data sector beyond the time to receive a next data sector. The error detection and correction device is coupled to sequentially receive a plurality data sectors from a data storage medium. The device includes a buffer and error detection and correction circuitry. The buffer is configured to sequentially receive and store the plurality of data sectors from the data storage medium. The error detection and correction circuitry is configured to sequentially receive the data sectors for sequentially detecting errors in each of the received data sectors. The error detection and correction circuitry corrects the detected errors in the associated sector that is stored in the buffer beyond the time to receive a next data sector in sequence.

Device and method for extending error correction beyond one sector time

Disclosed is a Chien search circuit for determining roots to an error locator polynomial that is defined by a set of coefficients. The circuit includes N sub-Chien search circuits, each of which is configured to sequentially evaluate a subset of field elements from a specified set of field elements. Each sub-Chien search circuit includes a set of storage elements, a set of constant multipliers, an adder, and a comparator. The set of storage elements stores a set of values, and receives and stores the set of coefficients as the set of values. One storage element is associated with each coefficient. The set of constant multipliers is coupled to receive the set of values from the set of storage elements. One constant multiplier is associated with one storage element. Each of the constant multipliers is associated with a constant field element and is configured to multiply the received value and the constant field element to generate a product. Each of the constant multipliers is coupled to feed the product back to the associated storage element for storage. The adder is coupled to receive the stored set of values from the set of storage elements for generating a sum of the set of values for a current field element being evaluated. The comparator is coupled to receive the sum for comparing the sum to a specified constant value. The comparator generates a signal indicating that the current field element is a root when the sum is equal to the specified constant value.

Parallel Chien search circuit

Encoders, syndrome generators, and methods for generating ECC check bytes and partial syndromes from a user data sector using a single RAM unit. The user data includes a plurality of data bytes. The encoder includes a storage unit and encoder circuitry. The storage unit is configured to receive and store a plurality of interim check bytes. The encoder circuitry is configured to receive the data bytes of the user data sector sequentially and the interim check bytes to generate a plurality of new interim check bytes in accordance with a generator polynomial. The new interim check bytes is generated after each data bytes of the data sector is received. The encoder circuitry is arranged to receive the interim check bytes from the storage unit such that the encoder circuitry generates the new interim check bytes and stores the generated new interim check bytes in the storage unit as the interim check bytes. The interim check bytes stored in the storage unit correspond to the ECC check bytes when the interim check bytes have been generated in response to all the bytes of the user data sector.

RAM based error correction code encoder and syndrome generator with

The present invention provides an apparatus for generating an error locator polynomial from a plurality of partial syndromes. The partial syndromes are generated from a data sector sequentially read from a storage medium. The apparatus comprises discrepancy circuitry, correction polynomial circuitry, connection polynomial circuitry, and a control circuitry. The discrepancy circuitry is configured to receive a selected partial syndrome for generating a discrepancy .DELTA..sup.(k). The correction polynomial circuitry is configured to receive the kth discrepancy .DELTA..sup.(k) from the discrepancy circuitry for generating an associated correction polynomial T(z). The connection polynomial circuitry is configured to receive the kth discrepancy .DELTA..sup.(k) from the discrepancy circuitry for generating an associated connection polynomial .LAMBDA..sup.(k) (z). The control circuitry provides sequencing and control signals to the discrepancy circuitry, the correction polynomial circuitry, and the connection polynomial circuitry in accordance with Berlekamp-Massey algorithm. The connection polynomial circuitry outputs the kth connection polynomial .LAMBDA..sup.(k) (z) as an error locator polynomial when k is equal to the total number of partial syndromes.

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Saratoga, CA, United States of America

Honda Yang