Texas Instruments Corporation

Hon W Lam

Ravishankar Sundaresan

Perry A Penz

James Thomas Carlo

Aloysious F Tasch, Jr

John M Pankratz

Ham-Tzong Yuan

A method for siliciding interconnects on a vertically integrated device utilizing stacked CMOS technology includes a step for blocking off the p-channel devices. This blocking step is utilized to block the p-channel device in a stacked CMOS pair prior to forming titanium di-silicide on the exposed polysilicon interconnects. A mask is formed on the top polysilicon layer that forms the p-channel device and then patterned to remove the mask and the top polysilicon layer to expose the underlying polysilicon layers. A sidewall oxide is then formed to completely seal the p-channel devices and then the exposed silicon and polysilicon surfaces subjected to a self-aligned silicide process.

Method for fabricating stacked CMOS transistors with a self-aligned

In stacked CMOS, a single gate in first level polycrystalline silicon is used to address both an N-channel device in the substrate and an overlaid p-channel device. The p-channel device has self-aligned source and drain regions formed by diffusing a dopant from doped regions underlying them. The doped regions are formed by planarizing a doped insulating layer, and etching the doped layer back to the upper level of the gate prior to deposition of a second polysilicon layer.

Method for source/drain self-alignment in stacked CMOS

A method of forming a semiconductor device having a single crystal silicon substrate, the surface of which includes exposed silicon areas bounded by and coplanar with insulating oxide regions. A polysilicon layer is deposited thereon and annealed to form a single crystal epitaxial region overlying the exposed substrate areas while the regions overlying the oxide areas in the substrate surface may be of polycrystalline form. This structure is applied to NMOS, CMOS, MESFET, and I.sup.2 L devices to achieve high packing density, high speed, improved isolation between devices and reduced susceptibility to latch-up.

Localized epitaxy for VLSI devices

Method of fabricating a display with silicon integrated circuits included on the same monolithic structure and the flat panel display produced thereby. The display which may be of the liquid crystal or electrochromic type, for example, is formed as an x-y matrix display having individual address transistors respectively asociated with each of the display units or pixels. The substrate is preferably of transparent material, such as quartz or a glass plate, on which a polysilicon layer is disposed. The polysilicon layer is patterned to provide a plurality of islands which are subjected to a laser annealing treatment at an intensity sufficient to cause recrystallization thereof. The polysilicon material in the islands is converted by the laser annealing to crystalline silicon having an enhanced electron mobility characteristic such that a matrix array of address transistors in the form of MOSFETS can be fabricated in the individual islands. Thereafter, elements of the display are formed in conjunction with the matrix array of address transistors, beginning with the formation of an array of metal electrodes in respective association with corresponding address transistors. Various peripheral circuits for the display, such as drive circuits, are formed in other islands of crystalline silicon resulting from the laser annealing of the polysilicon islands such that a monolithic structure including a display with silicon integrated circuits for operating the display is produced.

Method of fabricating display with semiconductor circuits on monolithic

A method for preparing semiconductor material for integrated circuit device fabrication. A retaining wall is formed around islands of semiconductor material that are to include the active devices, and the islands are then subjected to transient radiation annealing. The retaining wall holds the shape of the islands during annealing, and promotes uniform crystal alignment in the material.

Retaining wall technique to maintain physical shape of material during

A method for producing monocrystal on insulator is disclosed. Initially, an epitaxial layer is created on the single crystal substrate. This epitaxial layer may be formed by direct deposition of the monocrystal layer, or through epitaxial monocrystal growth induced after a polycrystal or amorphous layer has been deposited upon the substrate. By appropriately scanning a laser or other focused energy source beginning at some point within the epitaxial layer, and moving into the polycrystalline or amorphous layer over the insulator region, the polycrystalline or amorphous layer will melt, then upon resolidifying it will be monocrystal in structure due to its monocrystal neighbor, the epitaxial layer.

Method of producing monocrystal on insulator

A magnetic bubble detector comprising a planar layer of magnetic material in which magnetic bubble domains can be moved and a thin planar film on one surface of that layer. The layer has a magnetization perpendicular to the plane of the layer while the film has a magnetization in the plane thereof. The planar layer and film comprise an optical waveguide for propagation of linearly polarized light therethrough along a first axis. Linearly polarized light is coupled into the guide. A bubble expander stretches bubble domains in a direction transverse to their direction of movement as they are moved in the layer of magnetic material past the light guide on a second axis transverse the first axis. A sensor including a light coupling device for coupling light out of said waveguide senses changes in the polarization mode of the light propagating along the axis of the waveguide whereby the fringing field of the stretched bubble will modulate the polarized light propagating along the first axis and provide a light output signal from the sensor thereby indicating the passage of a magnetic domain.

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Dallas, TX, United States of America

Hon W Lam