International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Hon-Sum Philip Wong

Kevin K Chan

Phaedon Avouris

Jeffrey Bowman Johnson

Sudhir Muniswamy Gowda

Jungwook Yang

Chung H Lam

Guy M Cohen

Joerg Appenzeller

Hyun J Shin

Philip G Collins

Richard Martel

Peter Hong Xiao

Terence B Hook

Paul Michael Solomon

Yuan Taur

David V Horak

Christian Lavoie

Leland Chang

Xinlin Wang

Jia Chen

Roy Arthur Carruthers

Lijuan Huang

Edward J Nowak

Ramachandra Divakaruni

Arne Watson Ballantine

James William Adkisson

Fenton Read McFeely

Christopher Bruce Murray

David James Frank

Kathryn Wilder Guarini

Erin C Jones

Dale J Pearson

Stephen Scott Furkay

K Paul L Muller

Christopher G M M Detavernier

Huilong Zhu

Hendrik F Hamann

Jack Oon Chu

John Peter Karidis

Robert K Leidy

Robert H Dennard

John Albrecht Ott

Donald Francis Canaperi

K Paul Muller

Brian L Ji

Rama Nand Singh

Christopher Peter D'Emic

David R Hanson

Louis L C Hsu

Michelle Leigh Steen

Christophe Detavernier

Massimo V Fischetti

Ying L Yao

Steven E Laux

Mary Yvonne Lanzerotti

Mei Kei Ieong

Edwin Chih-chuan Kan

Christophe G M M Detavernier

Hendrick Hamann

Zhong John Deng

John Albert Ott

A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

Method of fabricating self-aligned nanotube field effect transistor

Self-aligned nanotube field effect transistor

A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Self-aligned process for nanotube/nanowire FETs

A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.

Phase change tip storage cell

Method of making integrated circuit (IC) including at least one storage cell

A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same.

Integrated circuit having gates and active regions forming a regular grating

Vertical nanotube field effect transistor

A multi-bit phase change memory cell including a stack of a plurality of conductive layers and a plurality of phase change material layers, each of the phase change material layers disposed between a corresponding pair of conductive layers and having electrical resistances that are different from one another.

Multi-bit phase change memory cell and multi-bit phase change memory including the same, method of forming a multi-bit phase change memory, and method of programming a multi-bit phase change memory

A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.

Connection device with actuating element for changing a conductive state of a via

A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read-write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit-read-write-search-line, and a drain connected to another end of the second phase change material element.

Non-volatile content addressable memory using phase-change-material memory elements

Growing community of inventors

Chappaqua, NY, United States of America

Hon-Sum Philip Wong