National Semiconductor Corporation

National Semiconductor Company

Hon Kin Chiu

Peyman Hojabri

Wai Cheong Chan

Vladislav Vashchenko

Robert Eddy

Leonard Stencel

Wayne Harlan

An integrated digitally controlled linear-in-decibels attenuator circuit in which one or more sets of selection switches establish a desired attenuation by selectively connecting the input signal electrode to one or more corresponding resistive ladder networks connected in series, thereby providing a substantially more constant signal attenuation value over a wider frequency bandwidth. With a single resistive ladder network, attenuation control is achieved using a thermometer switching code. With multiple resistive ladder networks, coarse and fine attenuation control can be achieved using thermometer and bubble switching codes, respectively.

Integrated digitally controlled linear-in-decibels attenuator

A method for addressing multiple instances of a same type of slave device on a bus is provided that includes receiving a plurality of unique device addresses at each of the slave devices and overwriting a default device address in each of the slave devices with a different one of the unique device addresses.

Method and system for addressing multiple instances of a same type of device on a bus

A level-shifting inverting circuit provides a blanking signal to Gridof a CRT. The circuit provides the blanking signal from a blanking logic signal according to a voltage transfer characteristic that is substantially similar to the voltage transfer characteristic of a standard CMOS inverter. Also, the level-shifting inverting circuit includes a switch circuit that includes a differential pair. The differential pair has the blanking logic signal at one input, and a bias signal at the other input. The switch circuit is coupled to a voltage divider that provides an output voltage that is pre-determined by a resistor ratio when the switch circuit is open. If the blanking logic signal is low, the switch circuit is open. Conversely, if the blanking logic signal is high, the switch circuit is closed, and sinks current from the voltage divider, causing the output voltage to correspond to a second pre-determined voltage level.

Method and apparatus for a level-shift inverter for cathode ray tube blanking

A differential amplifier circuit with a self-controlled common mode output voltage.

Differential amplifier with controlled common mode output voltage

Video signal control circuitry for use in a video display system in which a variation in a brightness level of a video display signal causes a corresponding variation in a beam current signal, wherein such video signal control circuitry maintains a controllable video display signal brightness level at a substantially constant average value notwithstanding a variation in the incoming video signal brightness level.

Video display signal brightness control circuit

A circuit for a digitally operating linear-in-decibels attenuator circuit controlled using an analog control signal. The attenuator circuit includes a resistor ladder, digitally controlled switches, and a flash analog-to-digital converter. The resistive ladder includes resistances coupled in series between an input and output electrode. The resistive ladder also includes shunt resistances, each of which is coupled to a corresponding series resistance and to a corresponding digitally controlled switch that is controlled by a corresponding digital control signal. Each of the switches include a pole electrode coupled to a corresponding shunt resistance and to the input electrode, and a throw electrode coupled to the corresponding shunt resistance and to the common node for attenuating voltage from an input signal. The flash analog-to-digital converter is controlled by an analog control signal and outputs digital control signals in a thermometer code for controlling the digitally controlled switches.

Circuit for controlling a linear-in-decibels attenuator circuit using an analog control signal

A charge pump-based PLL dynamically controls loop gain in response to the frequency of an input signal. The loop gain is dynamically adjusted by varying the bias current of the charge pump circuit of the PLL. The bias current is varied in response to the voltage of a loop filter that is coupled to the output of the charge pump circuit. A voltage-to-current converter ('V/I converter') converts the voltage of the loop filter to a current. The current is mirrored to a dynamic bias generator. The dynamic bias generator comprises a sample-and-hold circuit that is used to sample the mirrored current when the charge pump circuit is temporarily switched off. The sampled current level is used to adjust the level of the bias current of the charge pump circuit. The switching the charge pump off minimizes the disturbance of the loop filter voltage by the charge pump.

Charge pump-based PLL having dynamic loop gain

A circuit for horizontal deflection includes a first PLL circuit that is arranged to provide a first PLL output signal, and a second PLL circuit that is arranged to provide a second PLL output signal. A first PLL circuit is arranged to provide equalizing pulse removal. The first PLL circuit includes a gated PFD and an equalization pulse removal logic circuit. The equalization pulse removal logic circuit is arranged such that, if equalizing pulses occur in a sync signal, the gated PFD is gated during each equalizing pulse. The second PLL circuit is arranged to provide a wide capture range, and to lock a center of a pulse of the center of the feedback signal with the leading edge of the first PLL output signal. The second PLL circuit includes a frequency comparator circuit, a PFD, and a phase detector. The frequency comparator circuit is arranged to select either the PFD or the phase detector.

Circuit for two PLLs for horizontal deflection

A gated phase-frequency detector circuit includes a phase-frequency detector and a multiplexer circuit. The phase-frequency detector is arranged to provide UP and DOWN signals responsive to a reference clock signal and a feedback signal. Further, the phase-frequency detector includes a first flip-flop that provides the UP signal, a second flip-flop that provides the DOWN signal, and a clear logic circuit. One input of the multiplexer circuit is coupled to the output of the first flip-flop, another input of the multiplexer circuit is arranged to receive a logic high signal, and an output of the multiplexer circuit is coupled to the D input of the first flip-flop. The multiplexer circuit is arranged to multiplex the logic high signal and the UP signal responsive to a reference gate signal. If the reference gate signal corresponds to an active level, logic level of the UP signal does not change.

Phase-frequency detector with gated reference clock input

A phase-locked loop circuit is arranged for equalizing pulse removal. The phase-locked loop circuit includes a multi-phase pulse generator circuit that is arranged to provide a feedback signal and a gate signal from an output of a voltage-controlled oscillation circuit. The gate signal leads the feedback signal by approximately one-fourth of a period. Also, an equalizing pulse removal logic circuit is arranged to provide a sync gate signal from the feedback signal, the gate signal, and a sync signal. The sync gate signal is provided such that, if the sync signal includes equalizing pulses, the sync gate signal corresponds to an inactive logic level during the equalizing pulses. A phase-frequency detector of the phase-locked loop circuit is gated such that the phase-frequency detector is not changed by the sync signal if the sync gate signal corresponds to the inactive logic level.

Apparatus and method for PLL with equalizing pulse removal

A PLL circuit is arranged to provide a wide capture range, and to lock the leading edge of the feedback signal with the center of the reference clock pulse. The PLL circuit includes a charge pump circuit, a loop filter circuit, a VCO circuit, a PFD circuit, a phase detector circuit, a frequency comparator circuit, and a multiplexer circuit. The frequency comparator circuit is configured to compare the frequency of the reference clock with the frequency of the feedback signal, and to provide a status signal based on the comparison. The comparison is a determination of whether the frequencies of the reference clock and the feedback signal are within a tolerance window. Further, the multiplexer circuit selects either the PFD output or the phase detector output based on the comparison. The PFD is employed to bring the frequencies of the feedback signal and the reference clock signal within the tolerance window.

Wide frequency range phase-locked loop circuit with phase difference

The invention is directed to improving power consumption in an integrated circuit by reducing the leakage current of a plurality of MOS transistors with an adaptive back biasing circuit. Since the leakage current characteristic is often non-linear, the optimal back bias voltage (lowest leakage current) is typically identifiable at an inflection point in a graph of the leakage current characteristic versus back bias voltage. Also, depending upon the doping of the MOS transistors (N versus P type) and manufacturing variables for a particular fabrication process, the position of this inflection point can vary between individual integrated circuits that implement substantially the same arrangement of MOS transistors. Despite these issues, the inventive circuit can substantially reduce the leakage current by coupling an adjusted back bias voltage to the substrate of an Integrated Circuit. The invention provides an adjusted back bias voltage to the bulk terminals (substrate) based on a determination of the inflection point for the leakage current characteristic in an individual integrated circuit.

Adaptive threshold scaling circuit

A phase locked loop (PLL) system is arranged to automatically adjust the pre-scaler divide ratio. The PLL includes a phase-frequency detector circuit that compares a feedback clock signal to an input clock signal to provide UP and DOWN signals. A charge-pump circuit provides an oscillator control signal in response to UP and DOWN. A VCO produces an oscillator signal in response to the oscillator control signal. A first divider circuit provides an output clock signal in response to the oscillator signal, where an up-down counter circuit controls the divider ratio. A second divider circuit provides the feedback clock signal in response to the output clock signal. The up-down counter evaluates the output of the window comparator, which analyzes the oscillator control signal for proper operation with the VCO.

Automatic pre-scaler control for a phase-locked loop

A frequency comparator circuit is configured to compare whether the frequency of two input signals are within a tolerance of each other. The frequency comparator circuit includes two counter circuits, an AND gate, and a frequency detector circuit that is configured to provide two reset signals. The two counter circuits are arranged to be clocked by a respective one of the two input signals, and further arranged to be reset by a respective one of the two reset signals. Further, the AND gate is arranged to perform an AND function on the overflow outputs of the first and second counter circuits to provide an status signal. If the status signal is high, the difference in frequency between the two input signals is less than the tolerance. If the status signal is low, the difference in frequency between the two input signals exceeds the tolerance.

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Hayward, CA, United States of America

Hon Kin Chiu