Nvidia Corporation

Hon Fei Chong

David Wyatt

Mark Alan Overby

Benjamin K Dodge

Yu Qing Cheng

Rambod Jacoby

Tony Yuhsiang Cheng

Howard Tsai

Tsungyi Lin

Typical hybrid graphics systems operate in either a 'high-performance mode' or in an 'energy saver mode.' While operating in the high-performance mode, a discrete graphics processing unit (dGPU) performs high-performance graphics processing operations and also receives and satisfies access requests targeting a configuration space within the dGPU. While operating in the energy saver mode, an integrated graphics processing unit (iGPU) performs graphics processing operations and the dGPU is powered down. In this scenario, a system management unit (SMU) intercepts and satisfies access requests targeting the dGPU. Since access requests targeting the dGPU are satisfied while the dGPU is powered down, the dGPU continues to be enumerated in the system using the same system resources as originally granted, and can therefore be switched to for implementing high-performance mode more quickly than if it was removed, and required a complete plug-and-play re-enumeration and re-allocation of system resources.

System and method for masking transistions between graphics processing units in a hybrid graphics system

One embodiment of the present invention sets forth a technique for selecting a boot VGA adapter in a multiple VGA adapter system by controlling the system boot process using the VBIOS display detection service and boot flags that are stored in non-volatile platform memory. The SBIOS initiates a first boot that selects the motherboard integrated graphics processing unit (MGPU) as the boot VGA adapter. During this first boot, if the SBIOS determines that there are display devices attached to the MGPU, then the first boot completes normally. Otherwise, the SBIOS aborts the first boot and initiates a second boot that selects a secondary, discrete graphics processing unit GPU (DGPU) as the boot VGA adapter. During this second boot, if the SBIOS determines that there are display devices attached to the DGPU, then the second boot completes normally. Otherwise, the SBIOS aborts the second boot, and initiates and completes a third system boot that selects the MGPU as the boot VGA adapter while setting flags to ensure that the overall process does not repeat.

System and method for selecting the boot VGA adapter in a multi-graphics processing unit computing system

A computing system has a mode of operation in which at least two different memory parameter profiles are read by a BIOS to configure memory. In one implementation the memory parameter profiles are stored in a serial presence detect memory using an extended serial presence detect format.

Apparatus, system, and method for extended serial presence detect for memory performance optimization

One embodiment of the present invention sets forth a technique to determine a bus address for an add-in card on a System Management bus (SMbus) that includes a hybrid microcontroller (hEC) and discrete graphics processing unit (dGPU). A graphics driver requests the System Basic Input/Output System (SBIOS) for a list of available slave addresses. The graphics driver receives the list and selects an available slave address to be assigned to the hEC. The graphics driver assigns the selected address to the hEC through an Inter-Integrated Circuit bus backdoor. The graphics driver then passes the selected address back to the SBIOS and the selected address is removed from the list of available addresses. Advantageously, this approach to dynamically assigning bus addresses provides compatibility with different types of hECs as well as with different motherboard configurations and other SMbus devices.

System and method for determining a bus address on an add-in card

Methods, apparatuses, and systems are presented for dynamically overclocking a processor comprising operating the processor at a clock rate to run an executable program by using the processor to carry out a plurality of instructions associated with the executable program, while the processor is running the executable program, repeatedly monitoring at least one activity measure associated with a specific operation of the processor, wherein the at least one activity measure is generated from within the processor, evaluating the at least one activity measure to determine whether a predefined condition representing processor activity level is met, and, if the predefined condition is met, dynamically adjusting the clock rate of the processor to modify execution speed at which the processor carries out instructions.

Growing community of inventors

Campbell, CA, United States of America

Hon Fei Chong