Advanced Micro Devices Corporation

Homi E Nariman

H Jim Fulford

James Broc Stirton

Kevin R Lensing

Steven P Reeves

Charles E May

Sey-Ping Sun

Hartmut Ruelke

David E Brown

The present invention is generally directed to various methods of stepper exposure processes and tools, and system for accomplishing same. In one embodiment, the method comprises forming a grating structure comprised of a plurality of photoresist features above a semiconducting substrate, measuring at least one characteristic of at least one of the photoresist features at a plurality of locations within the grating structure, and determining if the measured characteristic of the photoresist features varies across the grating structure.

Methods of calibrating and controlling stepper exposure processes and tools, and system for accomplishing same

The present invention is directed to several inventive methods of monitoring anneal processes performed on implant regions, and a system for accomplishing same. In one aspect, the method comprises forming a first plurality of implant regions in a semiconducting substrate, performing at least one anneal process on implant regions, performing a scatterometric measurement of at least one of the implant regions after at least a portion of the anneal process is performed to determine a profile of the implant region and determining an effectiveness of the anneal process based upon the determined profile of the implant region. In other embodiments, one or more parameters of the anneal process may be varied on subsequently processed substrates based upon the determined efficiency of the anneal process.

Method of monitoring anneal processes using scatterometry, and system for performing same

The present invention is generally directed to various structures for analyzing electromigration, and methods of using same. In one illustrative embodiment, the method includes forming a grating structure above a semiconducting substrate, the grating structure being comprised of a plurality of conductive features, forcing an electrical current through at least one of the conductive features until a resistance of the conductive feature increases by a preselected amount, and performing at least one scatterometric measurement of the conductive feature to determine a critical dimension of the conductive feature. In another illustrative embodiment, the method includes forming a plurality of grating structures above a semiconducting substrate, each of the grating structures being comprised of a plurality of conductive features having the same critical dimension, the critical dimension of the features of each of the plurality of grating structures being different, and forcing an electrical current through at least one of the conductive features in each of the plurality of grating structures until a resistance of the conductive feature increases by a preselected amount.

Structures for analyzing electromigration, and methods of using same

The present invention is generally directed to various methods of using scatterometry for analysis of electromigration. In one illustrative embodiment, the method comprises forming a grating structure above a semiconducting substrate, the grating structure being comprised of a plurality of conductive structures, forcing an electrical current through at least one of the conductive structures and performing scatterometric measurements of at least one conductive structure to detect a change in shape of at least a portion of the conductive structure. In further embodiments, the method comprises determining a susceptibility of at least one conductive structure to electromigration based upon the detected change in shape of the conductive structure.

Method of using scatterometry for analysis of electromigration, and structures for performing same

In one illustrative embodiment, the method involves forming a ring oscillator that includes a first grating structure comprised of a plurality of gate electrode structures for a plurality of N-channel transistors and a second grating structure comprised of a plurality of gate electrode structures for a plurality of P-channel transistors, and measuring the critical dimension and/or profile of at least one of the gate electrode structures in the first grating structure and/or the second grating structure using a scatterometry tool. In another embodiment, the method further involves forming at least one capacitance loading structure, comprised of a plurality of features, as a portion of the ring oscillator, and measuring the critical dimension and/or profile of at least one of the features of the capacitance loading structure using a scatterometry tool.

Scatterometry structure with embedded ring oscillator, and methods of using same

In one illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a layer of polysilicon above the gate insulation layer, implanting a dopant material into the layer of polysilicon, forming an undoped layer of polysilicon above the doped layer of polysilicon and performing an etching process on the undoped layer of polysilicon and the doped layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode. In further embodiments, the method comprises forming a layer of refractory metal above the gate electrode and performing at least one heating process to form a metal silicide region on the gate electrode structure. In another illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a first layer of polysilicon above the gate insulation layer, implanting a dopant material into the first layer of polysilicon to form a doped region having a dopant concentration level in the layer of polysilicon, forming a second layer of polysilicon above the doped region of the first layer of polysilicon, the second layer of polysilicon having a dopant concentration level that is less than the dopant concentration level of the doped region in the first layer of polysilircon, and performing an etching process on the second layer of polysilicon and the doped region in the first layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode.

Method of making a shaped gate electrode structure, and device comprising same

The present invention is generally directed to a method and a structure for calibrating a scatterometry-based metrology tool used to measure dimensions of features on a semiconductor device. In one illustrative embodiment, the method comprises measuring a critical dimension of at least one production feature formed above a wafer using a scatterometry tool, measuring at least one of a plurality of grating structures formed above the wafer using the scatterometry tool, each of the grating structures having a different critical dimension, and correcting the measured critical dimension of the at least one production feature based upon the measurement of the at least one grating structure. In further embodiments, the method comprises forming a plurality of production features above a wafer, forming a plurality of grating structures above the wafer, each of the grating structures comprised of a plurality of features each having a target critical dimension that thereby defines a critical dimension of the grating structure, each of the grating structures having a different critical dimension, measuring a critical dimension of at least one of the production features using a scatterometry tool, measuring at least one of the grating structures using the scatterometry tool to determine a measured critical dimension of at least one feature of the at least one grating structure, and correcting the measured critical dimension of the at least one production feature based upon a comparison between the measured critical dimension of the at least one feature on the at least one grating structure and the target critical dimension of the feature on the at least one grating structure.

Method and structure for calibrating scatterometry-based metrology tool used to measure dimensions of features on a semiconductor device

The present invention is directed to several inventive methods for characterizing implant profiles. In one embodiment, the method comprises providing a semiconducting substrate, forming a first plurality of implant regions in the substrate, and illuminating at least one of the first plurality of implant regions with a light source in a scatterometry tool, wherein the scatterometry tool generates a profile trace corresponding to an implant profile of the illuminated implant region. The method further comprises creating at least one profile trace corresponding,to an anticipated profile of the implant region, wherein, in creating the profile trace, values of at least one of an index of refraction (n) and a dielectric constant (k) are varied, and comparing the generated profile trace to at least one created profile trace.

Method of measuring implant profiles using scatterometric techniques wherein dispersion coefficients are varied based upon depth

The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In one embodiment, the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.

Method of forming silicon oxynitride films

Methods of fabricating an isolation structure on a substrate are provided. In one aspect, a method of fabricating an isolation structure on a substrate is provided that includes forming a first insulating layer on the substrate wherein the first insulating layer has a first sidewall. A trench is formed in the substrate that has a second sidewall. A second insulating layer is formed in the trench. The second insulating layer displaces the second sidewall laterally. The first insulating layer is densified by heating to liberate gas therefrom and thereby move the first sidewall into substantial vertical alignment with the second sidewall. The risk of substrate attack due to trench isolation structure pullback is reduced. Trench edges are covered by thick isolation material.

Self-aligning silicon oxynitride stack for improved isolation structure

A semiconductor device and fabrication process are provided in which a patterned metal layer is formed over a polysilicon line. The polysilicon line is disposed on a substrate and may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and the patterned metal layer is formed over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the patterned metal layer may extend over the top of the second polysilicon line and interconnect the two polysilicon lines. A contact for the polysilicon line is coupled to the patterned metal layer. The use of a patterned metal line may provide a larger footprint for the contact then the underlying polysilicon line(s) and may decrease the sheet resistance to the polysilicon line(s).

Semiconductor device having patterned metal layer over a polysilicon line and method of fabrication thereof

A high-reliability damascene interconnect structure and a method for forming the same are provided. An interlevel dielectric is formed over a semiconductor topography, and trenches for interconnects and/or vias are formed in the interlevel dielectric. A trench liner may then be deposited, followed by deposition of a low-resistance metal such as copper. The low-resistance metal deposition is preferably stopped before the trenches are entirely filled. Portions of the metal and trench liner external to the trenches are subsequently removed, such that low-resistance metal interconnect portions are formed. A high-melting-point metal, such as tungsten, is deposited over upper surfaces of the interconnect portions and interlevel dielectric. Portions of the high-melting-point metal are removed to form interconnects having a low-resistance metal lower portion and a high-melting-point metal upper portion. In one embodiment, the extrusion-prone lowresistance metal is removed from the vicinity of a ready extrusion path between the interlevel dielectric and an overlying dielectric. In another embodiment, the overlying metal is believed to prevent extrusion of the low-resistance metal by bonding with the low-resistance metal and by altering the electric field distribution between adjacent interconnects.

High-reliability damascene interconnect formation for semiconductor

A semiconductor device and manufacturing method is provided in which asymmetric source/drain regions are formed using a self aligning implant mask. A gate electrode is formed on a substrate and a dielectric layer is formed over the substrate and adjacent the gate electrode. A masking layer is formed over the dielectric layer and the gate electrode and selectively removed to form an implant mask. The implant mask extends further over a first side of the gate electrode than a second side of the gate electrode. Using the implant mask for alignment, a dopant is implanted into the active regions of the substrate adjacent the gate electrode to form a first heavily-doped region adjacent the first side of the gate electrode and second heavily-doped region adjacent the second side of the gate electrode. The first heavily-doped region is spaced further from the gate electrode than the second heavily-doped region. Contacts may be formed to the masking layer or a silicide layer formed from the masking layer.

Semiconductor device having self-aligned asymmetric source/drain regions

A semiconductor device and fabrication process are provided in which a polysilicon line is disposed on a substrate of the semiconductor device. The polysilicon line may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and an extended silicide layer is formed over the polysilicon line. The extended silicide layer may be formed by forming a patterned metal layer over the polysilicon line, forming a polysilicon layer over the patterned metal layer, and reacting the patterned metal layer with the polysilicon layer to form the extended silicide layer over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the silicide layer may extend over the top of the second polysilicon line and interconnects the two polysilicon lines.

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Austin, TX, United States of America

Homi E Nariman