Infineon Technologies Ag

Infineon Technologies Austria Ag

Holger Torwesten

Manfred Schneegans

Petteri Palm

Manfred Mengel

Martin Seck

Thomas Goebel

Markus Schwerd

Johann Helneder

Andrea Mitchell

Heinrich Körner

Juergen Hoegerl

Alexander Heinrich

Swee Kah Lee

Karsten Guth

Andre Arens

Soon Lock Goh

Grit Sommer

Alfred Martin

Manfred Schindler

Barbara Hasler

Stephan Dertinger

Florian Binder

Boris Plikat

Tobias Simbeck

Stefan Schmid

Thomas Göbel

A semiconductor module is disclosed. In one example, the module includes a carrier, at least one semiconductor transistor disposed on the carrier, at least one semiconductor diode disposed on the carrier, at least one semiconductor driver chip disposed on the carrier, a plurality of external connectors, and an encapsulation layer covering the carrier, the semiconductor transistor, the semiconductor diode, and the semiconductor driver chip. The semiconductor transistor, the semiconductor diode, and the semiconductor driver chip are arranged laterally side by side on the carrier.

Semiconductor module comprising transistor chips, diode chips and driver chips arranged in a common plane

A method of manufacturing semiconductor modules includes providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer, attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil, and encasing the semiconductor dies attached to the metal foil in an electrically insulating material. The metal layer and the metal foil are structured after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer. The electrically insulating material is divided along the surface regions devoid of the metal foil and the metal layer to form individual modules.

Semiconductor modules with semiconductor dies bonded to a metal foil

In an embodiment, an electronic component includes a dielectric layer having a first surface and a second surface, one or more semiconductor dies embedded in the dielectric layer and at least one electrically conductive member. The electrically conductive member includes a first portion and a second portion. The first portion includes a foil including a first metal and the second portion includes an electrodeposited layer including a second metal. The first portion and the second portion are embedded in the dielectric layer.

Electronic component

A method for manufacturing a chip package is provided, the method including: forming a layer arrangement over a carrier; arranging a chip including one or more contact pads over the layer arrangement wherein the chip covers at least part of the layer arrangement; and selectively removing one or more portions of the layer arrangement and using the chip as a mask such that at least part of the layer arrangement covered by the chip is not removed.

Method for manufacturing a chip package

In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer.

Power semiconductor module, method for producing a power semiconductor module, and semiconductor chip

Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.

Chip package and method of forming the same

An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.

Electronic device

An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

Integrated circuit with capacitor and method for the production thereof

A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material.

Substrate with feedthrough and method for producing the same

An electronic device and the production thereof is disclosed. One embodiment includes an integrated component having a layer containing a nickel-palladium alloy.

Growing community of inventors

Wuppertal, Germany

Holger Torwesten