Infineon Technologies Ag

Infineon Technologies Austria Ag

Holger Huesken

Hans-Joachim Schulze

Frank Dieter Pfirsch

Stephan Voss

Anton Mauder

Wolfgang Roesner

Peter Tuerkes

Gerald Deboy

Johannes Georg Laven

Armin Willmeroth

Francisco Javier Santos Rodriguez

Franz-Josef Niedernostheide

Roman Baburske

Peter Irsigler

Christian Philipp Sandow

Erich Griebl

Carsten Schaeffer

Manfred Pfaffenlehner

Philip Christoph Brandt

Roman Roth

Thomas Laska

Wolfgang Wagner

Alice Pei-Shan Hsieh

Viktoryia Lapidus

An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.

Semiconductor device having contact layers and manufacturing method

A power semiconductor device includes a semiconductor substrate with an edge termination region between an active region and a lateral rim. Non-metallic electrodes extend in the edge termination region on a front side of the substrate, and include at least three spaced apart non-metallic electrodes. One non-metallic electrode is an inner non-metallic electrode having an inner edge. Another non-metallic electrode is an outer non-metallic electrode having an outer edge. The shortest distance between the inner edge of the inner non-metallic electrode and the outer edge of the most non-metallic electrode is defined as distance p. Each non-metallic electrode is electrically connected to a respective doping region of the substrate by at least two respective metallic plugs each extending through a respective first opening formed in an electrically insulating bottom layer. The shortest distance d between any two metallic plugs of different non-metallic electrodes is larger than the distance p.

Power semiconductor device

Semiconductor device including first and second contact layers and manufacturing method

A method for manufacturing a power semiconductor device includes: forming a drift region of a first conductivity type, a second emitter region of a second conductivity type, a pn-junction between the second emitter region and drift region, and a first emitter region having a first doping region of the first conductivity type and a second doping region of the first conductivity type; forming a first emitter metallization in contact with the first emitter region to form an ohmic contact between the first emitter metallization and the first doping region, and to form a non-ohmic contact between the first emitter metallization and the second doping region; and forming a second emitter metallization in contact with the second emitter region. The first emitter region is formed using a mask that is aligned with respect to the second emitter region, so that the first and second doping regions are formed in aligned relation.

Method for manufacturing a power semiconductor device

A semiconductor device comprising a source region being electrically connected to a first load terminal (E) of the semiconductor device and a drift region comprising a first semiconductor material (M) having a first band gap, the drift region having dopants of a first conductivity type and being configured to carry at least a part of a load current between the first load terminal (E) and a second load terminal (C) of the semiconductor device, is presented. The semiconductor device further comprises a semiconductor body region having dopants of a second conductivity type complementary to the first conductivity type and being electrically connected to the first load terminal (E), a transition between the semiconductor body region and the drift region forming a pn-junction, wherein the pn-junction is configured to block a voltage applied between the first load terminal (E) and the second load terminal (C). The semiconductor body region isolates the source region from the drift region and includes a reduced band gap zone comprising a second semiconductor material (M) having a second band gap that is smaller than the first band gap, wherein the reduced band gap zone is arranged in the semiconductor body region such that the reduced band gap zone and the source region exhibit, in a cross-section along a vertical direction (Z), at least one of a common lateral extension range (LR) along a first lateral direction (X) and a common vertical extension range (VR) along the vertical direction (Z).

Semiconductor device with a reduced band gap zone

A power semiconductor device includes a semiconductor substrate layer of a first conductive type which has a lower part semiconductor layer of a second conductive type and an active region that includes a body region of the second conductive type, a source region of the first conductive type disposed in the body region, and a first doped region of the first conductive type at least a part of which is disposed below the body region. An emitter electrode is electrically connected to the source region, and a groove extends into the substrate layer and includes a shielding electrode electrically connected to the emitter electrode. The groove extends to a deeper depth into the substrate layer than the first doped region. At least a part of a gate is formed above at least a part of the source region and the body region, and is electrically insulated from the shielding electrode.

A transistor device includes an individual transistor cell arranged in a transistor cell field on a semiconductor body, the individual transistor cell having a gate electrode. The transistor device further includes a gate contact, electrically coupled to the gate electrode and configured to switch on the individual transistor cell by providing a gate current in a first direction and configured to switch off the individual transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction. The transistor device also includes a gate-resistor structure monolithically integrated in the transistor device. The gate-resistor structure provides a first resistance for the gate current when the gate current flows in the first direction, and provides a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Transistor device with integrated gate-resistor

A semiconductor device includes an active region and a semiconductor substrate layer having a lower part semiconductor layer of a second conductivity type. The active region includes a drift region formed by at least a part of the substrate layer, a body region of the second conductivity type formed on at least a part of the drift region, a source region of a first conductivity type disposed in the body region, and a first doped region of the first conductivity type at least partially disposed under the body region. A groove extends downward from a top of the substrate layer and contains a shielding electrode. A depth of the groove is greater than that of the first doped region. A gate at least partially formed above at least a part of the source region and the body region is electrically insulated from the shielding electrode.

A semiconductor body of an IGBT includes: a first base region of a second conductivity type; a source region of a first conductivity type different from the second conductivity type and forming a first pn-junction with the first base region; a drift region of the first conductivity type and forming a second pn-junction with the first base region; a collector region of the second conductivity type; at least one trench filled with a gate electrode and having a first trench portion of a first width and a second trench portion of a second width, the second width being different from the first width; and a field stop region having the first conductivity type and located between the drift region and the collector region. The field stop region includes a plurality of buried regions having the second conductivity type.

Insulated gate bipolar transistor

A semiconductor device includes a pn junction between a drift zone and a charge-carrier transfer region in a semiconductor body. An access channel provides a permanent charge carrier path connecting the drift zone with a recombination region through a separation region between the drift zone and the recombination region. The access channel adjusts a plasma density in the drift zone and the recombination region.

Semiconductor device with recombination region

A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Power MOS transistor with integrated gate-resistor

Embodiments relate to a semiconductor device, a semiconductor wafer structure, and a method for manufacturing or forming a semiconductor wafer structure. The semiconductor device includes a semiconductor substrate with a first region having a first conductivity type and a second region having a second conductivity type. The semiconductor device further includes an oxide structure with interrupted areas and a metal layer structure being in contact with the second region at least at the interrupted areas of the oxide.

Semiconductor device, a semiconductor wafer structure, and a method for forming a semiconductor wafer structure

A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.

Power semiconductor diode, IGBT, and method for manufacturing thereof

An IGBT with monolithic integrated antiparallel diode has one or more emitter short regions forming the diode cathode in the region of the high-voltage edge. The p-type emitter regions of the IGBT have no emitter shorts. The counterelectrode of the diode exclusively comprises p-type semiconductor wells on the front side of the device. Particularly in applications, such as lamp ballast, in which the diode of the IGBT is firstly forward-biased, hard commutation is not effected and the current reversal takes place relatively slowly. The emitter short regions may be strips or points below the high-voltage edge. The horizontal bulk resistance is increased and the snapback effect is reduced without reducing the robustness in the edge region. In a second embodiment, the IGBT is produced using thin wafer technology and the thickness of the substrate defining the inner zone is less than 200 &#x3bc;m. The thickness of the emitter region or of the emitter regions and short region(s) is less than 1 &#x3bc;m. A transparent emitter is preferable in this case.

IGBT with monolithic integrated antiparallel diode

A circuit configuration is used for off-load switching. The circuit configuration can be used as a component in a switch mode power supply, a clocked supply, a voltage regulator, and a lamp switch, wherein the circuit configuration is embodied as an IGBT, especially a field stop IGBT or alternately and additionally as a PT IGBT. A method for using the circuit configuration include three operating modes: in a first operating mode, power for a load is modulated by pulse modulation; in a second operating mode, the power is modulated by changing a switching-on time; and, in a third operating mode, both are implemented.

Circuit configuration for off-load switching, switch mode power supply, clocked supply, voltage regulator, lamp switch, and methods for operating the circuit configuration

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Munich, Germany

Holger Huesken