Hewlett-Packard Company

Hewlett-Packard Corporation

Verigy (Singapore) Pte. Ltd.

Holger Engelhard

Jochen Rivoir

Barbara Jean Duffner

Bradley D Pace

A method for converting a digital signal to an analog signal, said method including a plurality of signal sources, preferably current sources, one or more of said signal sources being variable output signal magnitude sources, said method including the steps of setting the output signal magnitudes of the one or more variable output signal magnitude sources by individual setting signals being input signals for said respective variable output signal magnitude sources, wherein said conversion is adaptable on a per signal basis in response to needs concerning bandwidth and/or accuracy for achieving a trade-off between sample-rate and resolution of said conversion.

Digital to analog conversion using summation of multiple DACs

Disclosed herein is a differential CMOS cell that achieves faster switching speeds than conventional CMOS logic by 1) biasing a differential pair of output nodes to a relatively high logic low voltage threshold, and 2) pulling up the differential pair of output nodes to a logic high voltage level. The differential CMOS cell is designed such that the difference between logic low and logic high voltage thresholds is much less than in traditional CMOS circuits (i.e., approximately 0.8 V-1.0 V as compared to 2.6 V). A lower voltage swing allows for fast switching of a differential output signal. In a preferred embodiment, the differential CMOS cell receives a primary differential input signal, and respective first and second secondary differential input signals. The differential CMOS cell includes a differential pair of arm circuits, each comprising a primary input switch for receiving a component of the primary differential input signal, and a differential pair of secondary input switches for receiving either the first or second secondary differential input signal. Each arm circuit is coupled between a current source and a voltage source. In operation, the primary differential input signal selects one of the first or second secondary differential input signals to be output as the differential output signal.

Differential CMOS logic family

A formatter circuit for generating pulses of a variable, in particular extremely short width comprises an input terminal (10) receiving a pulse start signal which is fed to a frequency divider circuit (11) and another input terminal (12) receiving a pulse-stop signal which is fed to a second frequency divider circuit (13). One of these frequency divider circuits generates two internal signals which are fed to a multiplexing circuitry (16, 17, 18), whereas the other frequency divider circuit generates at least one signal which is the control signal for said multiplexing circuitry. (FIG. 3).

Growing community of inventors

Nufringen, Germany

Holger Engelhard