Micro Technology, Inc.

Mti Technology Corporation

Sf2 Corporation

MIT Technology Corp.

Hoke S Johnson, Iii

David H Jaffe

Chris W Eidler

Joseph S Glider

Kaushik S Shah

Thomas E Idleman

David T Powers

Larry P Henson

Edward E Asato

Duc H Trang

A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller.

Apparatus and method for controlling data flow between a computer and

A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.

Method and apparatus for scheduling access to a CSMA communication medium

A block transfer data bus having two separate paths, with each element coupled to the bus having the ability to arbitrate for use of one or the other or both of the bus halves. Each bus half includes an address/data bus portion for sending/receiving the data and addresses. A separate control bus portion for each bus half provides certain status signals and a code indicating the type of data on the address/data bus. An arbitration bus provides data request signals from each element to a central arbiter. In addition, a separate grant signal associated with each bus half is provided back to each element from the arbiter along the arbitration bus. A line on each control signal bus indicates whether or not the bus half is busy.

Dual channel data block transfer bus

Method and apparatus for scheduling access to a CSMA communication

A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.

Method and apparatus for transferring data through a staging memory

A circuit for decoding a high speed Manchester encoded digital communication signal is provided. The circuit includes a pair of latch circuits which are used to detect clock edges in the encoded signal for providing respectively set and reset pulses to a third latch circuit, an output of which comprises the decoded data of the Manchester code signal. Additional logic is provided to extract a clock signal from the Manchester code signal.

Method and circuit for decoding a Manchester code signal

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Monte Sereno, CA, United States of America

Hoke S Johnson, Iii