Hong Kong Applied Science and Technology Research Institute Company, Limited

Hok Mo Yau

Kwok Kuen David Kwong

Kam Chuen Wan

Kwai Chi Chan

Ho Ming (Karen) Wan

Yat To William Wong

Ho Ming Karen Wan

Yat To (William) Wong

Tin Ho (Andy) Wu

Sze Wing Leung

Guang Jie Cai

Tin Ho Andy Wu

A bio-sensing processor chip acts as an auto-configurable platform to support a wide variety of bio-sensors. Nano-wires with attached bio-receptors for specific bio-molecules, ECG, and SPO2 bio-sensors drive analog voltages or currents to analog inputs of the bio-sensing processor chip. These analog inputs are divided into three sections. An input sensor detector/decoder detects which analog inputs are active and configures an analog-to-digital converter (ADC) to convert first-section inputs to 12 digital bits, second-section inputs to 16 bits, and third-section inputs to 20 bits. An Analog Front-End (AFE) is bypassed for the first section inputs but amplifies and filters second and third section inputs. A Universal Asynchronous Receiver Transmitter (UART) sends the converted digital values to a nearby external device using NFC or WiFi transmitters. When no battery is detected, energy is harvested from NFC signals from the external device, and one-shot measurements are made.

Self-powered and battery-assisted CMOS wireless bio-sensing IC platform

A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.

Parallel pipelined calculation of two calibration values during the prior conversion cycle in a successive-approximation-register analog-to-digital converter (SAR-ADC)

A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.

Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC

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Hong Kong, China

Hok Mo Yau