Samsung Electronics Co., Ltd.

Hoin Lee

Kiseok Lee

Chan-Sic Yoon

Jemin Park

Yoosang Hwang

Bong-Soo Kim

Jun Ho Lee

Keunnam Kim

Dongoh Kim

Sungho Jang

Augustin Jinwoo Hong

Juik Lee

Sooho Shin

Kwangmin Kim

Ilyoung Moon

Kiwook Jung

Bumseok Seo

Seungjin Kim

Jeon Il Lee

Jung-Bum Lim

Sangchul Yang

A semiconductor device includes a vertical stack of ring-shaped electrodes that are electrically connected together into a top electrode of a capacitor, on a semiconductor substrate. A bottom electrode of the capacitor is also provided, which extends vertically in a direction orthogonal to a surface of the substrate and through centers of the vertical stack of ring-shaped electrodes. An electrically insulating bottom supporting pattern is provided, which extends between a lowermost one of the ring-shaped electrodes and an intermediate one of the ring-shaped electrodes.

Semiconductor devices having highly integrated capacitors therein

A semiconductor device includes lower electrodes, a first supporter structure including first supporter patterns interconnecting the lower electrodes, wherein side surfaces of the first supporter patterns and side surfaces of the lower electrodes that are exposed by the first supporter patterns at least partially define a first open region, the first supporter patterns being spaced apart from one another, the first open region extending among the first supporter patterns in a horizontal direction, a dielectric layer covering the first supporter structure and the lower electrodes, and an upper electrode on the dielectric layer. A distance between adjacent ones of the first supporter patterns is smaller than or equal to a pitch of the lower electrodes.

Semiconductor devices having supporter structures

A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

Semiconductor memory device

A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

Semiconductor devices with alignment keys

Semiconductor memory device and method of manufacturing the same

Growing community of inventors

Suwon-si, South Korea

Hoin Lee