Samsung Electronics Co., Ltd.

Sungkyunkwan University

Hoijin Lee

Bai-Sun Kong

Gunok Jung

Seok-il Kwon

Seok Il Kwon

Hyejoo Lee

An integrated circuit includes an intellectual property (IP) block including a plurality of standard cells. A first power gating cell supplies power to the IP block via a first power rail extending in a first horizontal direction. A first conductive line extends in a second horizontal direction perpendicular to the first horizontal direction in a first metal layer. A second power gating cell is arranged adjacent to the first power gating cell in the second horizontal direction to supply power to the IP block via a second power rail extending in the first horizontal direction. A second conductive line extends in the second horizontal direction in the first metal layer. The first conductive line is coupled with the second conductive line in the second horizontal direction.

Superpower gating cell and integrated circuit including the same

A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.

Power gate switching system

A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.

Clock gated circuit and digital system having the same

The function of logic cells may be changed by altering their metal routing. Logic cells altered in this manner may be used to correct, substitute, or otherwise alter the operation of logic blocks or scan paths without completely re-working an integrated circuit. The process may be referred to as an engineering change order (ECO) process. According to an exemplary process a buffer may be reconfigured to operate as a NAND gate, a NOR gate, or an INVERTER, for example, and may be configured to operate in a circuit in need of such a logic function.

Eco logic cell and design change method using eco logic cell

An integrated circuit device includes first and second latches (e.g, D-type flip flops) responsive to a clock signal. Each of the first and second latches respectively includes a data input terminal, a scan input terminal, a scan enable terminal and an output terminal. A combinational logic circuit may be provided, which is configured to receive the signal from the output terminal of the first latch and configured to generate a signal at the data input terminal of the second latch. A scan path is also provided, which is responsive to a scan enable signal. The scan path is configured to selectively pass a signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is active. A power saving switch is also provided. This switch, which is responsive to the scan enable signal, includes a first current carrying terminal electrically coupled to the scan path. The switch is configured to disable the scan path from passing the signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is in an inactive state.

Integrated circuit devices having selectively enabled scan paths with power saving circuitry

A flip-flop circuit includes an input portion that receives a first external input signal through a first external input terminal, a storage portion that stores a signal transmitted from the input portion, and an output portion that outputs the signal stored in the storage portion through an external output terminal as a logic operation result with respect to a second external input signal received through a second external input terminal of the input portion. The output portion includes a logic gate directly connected to the external output terminal and an input terminal of the logic gate receives the signal stored in the storage portion.

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Seoul, South Korea

Hoijin Lee