Samsung Electronics Co., Ltd.

Hoi-ju Chung

Sang-Uhn Cha

Hyun-Joong Kim

Ho-Young Song

Jong-Pil Son

Seong-Jin Jang

Jae-Youn Youn

Kwang-il Park

Chul-woo Park

Hak-soo Yu

Hyo-Jin Kwon

Su-a Kim

Ye-Sin Ryu

Yong-jun Lee

Yong-Jin Kwon

Hyo-jin Choi

Eun-Hye Park

Mu-jin Seo

Young-Soo Sohn

Chul-Sung Park

Jang-Woo Ryu

Gong-Heum Han

Seong-Jin Cho

Ju-yun Jung

Tae-Seong Jang

Sung-Hoon Kim

Young-il Kim

Tae-Young Oh

Jae-Wook Lee

Byung-Jun Min

Young-Yong Byun

Chan-yong Lee

Chae-Hoon Kim

Seong-Hyun Jeon

Seo-Hee Kim

A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Semiconductor memory devices, memory systems including the same and methods of operating memory systems

A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.

Characterization of in-chip error correction circuits and related semiconductor memory devices/memory systems

A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices

A semiconductor memory device includes a memory cell array and a main controller. The memory cell array includes a plurality of memory bank arrays, and each of the memory bank arrays includes a plurality of pages. The main controller counts a number of accesses to a first memory region of the memory cell array, generates at least one victim address of at least one neighbor memory region that is adjacent to the first memory region and performs a scrubbing operation sub-pages of the pages corresponding to the at least one victim address when the counted number of accesses reaches a first reference value during a reference interval.

Semiconductor memory devices, memory systems including the same and methods of operating the same

A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit performs an error correction code (ECC) encoding on write data to be stored in the memory cell array, and performs an ECC decoding on read data from the memory cell array. The control logic circuit controls access to the memory cell array and generates an engine configuration selection signal based on a command. The error correction circuit reconfigures a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal.

Semiconductor memory devices and memory systems including the same

A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.

Semiconductor memory devices and methods of operating the same

Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.

Memory device and memory system performing request-based refresh, and operating method of the memory device

A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.

A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

Semiconductor memory devices, memory systems including the same and method of correcting errors in the same

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Hoi-ju Chung