Microsoft Technology Licensing, LLC

Hoi Huu Vo

Andrew James Edwards

Hon Keat W Chan

David Mitford Gillies

Amitabh Srivastava

Jiyang Liu

Darko Kirovski

Ronnie Chaiken

Samer Arafeh

Carlos P Gomes

Milenko Drinic

Ken B Pierce

Mark L Roberts

John A Lefor

Patrick L McDonald

Gideon Andreas Yuval

Forrest Curtis Foltz

Vivek Bhanu

Yimin Deng

Steven J Pratschner

Danny Chen

Yue Zuo

Vivek P Divakara

Allan James Murphy

Bruce M Kuramoto

Hoyuen Chau

Jay Krell

Gregory A Eigsti

Galen Clyde Hunt

Adrian Mihail Marinescu

Zheng Wang

Garret Buban

Thomas Dee McGuire

David Bradley Probert, Jr

Jonathan David Morrison

HoYuen Chau

Eduardo A Cuervo Laffaye

Ho Yuen Chau

Joe Chau

Hon Keat Chan

Paul V Donlan

Samer N Arafeh

A server computing device for inducing latency on target input streams is provided. The server computing device includes a processor configured to receive a plurality of input streams from a respective plurality of client computing devices. Each input stream includes a plurality of inputs controlling actions of respective characters in a multiplayer online software program. The processor is further configured to determine a latency of each of the input streams, identify a higher latency input stream and a lower latency input stream among the plurality of input streams, and induce a higher latency in the lower latency input stream to narrow a difference in latency between the higher latency input stream and the lower latency input stream.

Inducing higher input latency in multiplayer programs

High-performance tracing can be achieved for an input program having a plurality of instructions. Techniques such as executable instruction transcription can enable execution of a plurality of instructions at a time via a run buffer. Execution information can be extracted via run buffer execution. Fidelity of execution can be preserved by executing instructions on the target processor. Other features, such as an executable extraction instruction ensemble, branch interpretation, and relative address compensation can be implemented. High quality instruction tracing can thus be achieved without the usual performance penalties.

High-performance processor instruction tracing

Methods for dynamically instrumenting a program while the program is executing are described. In some embodiments, profiling hooks may be selectively inserted into and removed from a program while the program is running. The hooks may gather profiling information, such as the frequency and duration of function calls, for a selected set of functions. The hooks may be inserted into the program without requiring a special build or modifications to the binary by modifying machine-level instructions for the program stored in system memory. The ability to selectively insert instrumentation into the machine-level instructions stored in the system memory allows a set of functions to be selected during execution of the program and hooks for each function of the set of functions to be dynamically inserted or removed during execution of the program to precisely capture profiling information for the set of functions.

Function-level dynamic instrumentation

Computerized methods, systems, and computer-storage media for allowing virtual machines (VMs) residing on a common physical node to fairly share network bandwidth are provided. Restrictions on resource consumption are implemented to ameliorate stressing the network bandwidth or adversely affecting the quality of service (QoS) guaranteed to tenants of the physical node. The restrictions involves providing a scheduler that dynamically controls networking bandwidth allocated to each of the VMs as a function of QoS policies. These QoS policies are enforced by controlling a volume of traffic being sent from the VMs. Controlling traffic includes depositing tokens into token-bucket queues assigned to the VMs, respectively. The tokens are consumed as packets pass through the token-bucket queues. Upon consumption, packets are held until sufficient tokens are reloaded to the token-bucket queues.

Applying policies to schedule network bandwidth among virtual machines

A method prepares a computer program for operation in a computer supply system that supplies portions, or program units, of program code or program data of the computer program as the program needs the portions. The method includes defining a program unit of the program and removing the program unit from the program, thereby producing a program skeleton that is missing the program unit. The method further includes inserting instructions in place of the program unit in the program skeleton. The instructions are operative to request the program unit when the program skeleton encounters the instructions. An information structure includes a program skeleton of a program. The program skeleton is missing a funclet of the program, but includes a placeholder in place of the funclet. The program skeleton additionally includes instructions in place of the funclet. The instructions are operative to request the funclet when the program skeleton encounters the instructions.

Preparation for software on demand system

An application compatibility module is disclosed that provides compatibility between legacy binary system modules ('legacy binaries') and a native operating system. The application compatibility module therefore allows legacy applications to execute within the native operating system, while still using their corresponding legacy binaries. The application compatibility module may provide compatibility between legacy binaries and the native operating system by translating communications between the legacy binaries and the native operating system.

Environment for executing legacy applications on a native operating system

A system and method for automatically updating software components on a running computer system without requiring any interruption of service. A software module is hotpatched by loading a patch into memory and modifying an instruction in the original module to jump to the patch. A coldpatching technique places a coldpatch version of the module on disk for subsequent loading by processes, after hotpatching occurred. The coldpatch has the entry points to its functions at the same relative locations within the module as the hotpatch, which facilitates subsequent hotpatching. A hotpatch and coldpatch are automatically generated by deriving differences between changed and original binary files, and establishing the point to insert the jump. Validation is performed to ensure that the hotpatch is applied to the correct version, and that the coldpatch is replacing the correct version. Version management is also provided to control the number of patches via support rules.

Patching of in-use functions on a running computer system

Compression and decompression of data such as a sequential list of executable instructions (e.g., program binaries) by uniformly applying a predictive model generated from one segment of the executable list as a common predictive starting point for the other segments of the executable list. This permits random access and decompression of any segment of the executable list once a first segment (or another reference segment) of the executable list has been decompressed. This means that when executing an executable list (e.g., an executable file), a particular segment(s) of the executable list may not need to be accessed and decompressed at all if there are no instructions in that particular segment(s) that are executed.

Parallel predictive compression and access of a sequential list of executable instructions

Compressing program binaries with reduced compression ratios. One or several pre-processing acts are performed before performing compression using a local sequential correlation oriented compression technology such as PPM, or one of its variants or improvements. One pre-processing act splits the binaries into several substreams that have high local sequential correlation. Such splitting takes into consideration the correlation between common fields in different instructions as well as the correlation between different fields in the same instruction. Another pre-processing reschedules binary instructions to improve the degree of local sequential correlation without affecting dependencies between instructions. Yet another pre-processing act replaces common operation codes in the instruction with a symbols from a second alphabet, thereby distinguishing between operation codes that have a particular value, and other portions of the instruction that just happen to have the same value. Local sequential correlation compression such as PPM is then performed.

Compression of program instructions using advanced sequential correlation

A method of supplying program units of a computer program as the program needs the program units includes running a program skeleton. The program skeleton is derived from the program, but has a program stub where a program unit associated with the program stub may be inserted. Upon encountering the program stub, the method includes getting the program unit associated with the program stub and inserting the program unit at the program stub. A method of supplying funclets of a computer program from a server computer system to a client computer system includes receiving a plurality of requests for funclets during a test period. If a tested probability of requests for a first funclet being followed by requests for a second funclet is at least a predetermined probability, then the method also includes sending the first funclet and the second funclet to the client computer system in response to a request from the client computer system for the first funclet after the test period.

Software on demand system

Each component binary in a heterogeneous program is translated from a platform-specific instruction set into a set of intermediate representation (IR) instructions that are platform-neutral. The IR instructions are grouped into IR code blocks, the IR code blocks into IR procedures, and the IR procedures into IR components to create an intermediate representation hierarchy for the program. An application program interface is provided that permits user access to the IR hierarchy for instrumentation, optimization, navigation, and manipulation of the IR hierarchy. The transformed IR hierarchy is then translated into platform-specific instructions and output as a modified binary. The user can designate a different platform for the output translation of a code block than the platform for which the code block was originally written. Prologue and epilog code is added to contiguous blocks that are translated into different architectures. The modified binary can be iterated through the translation and transformation process to produce multiple versions of the heterogeneous program.

Translation and transformation of heterogeneous programs

Rapid determination of placement for code and data for optimal access of the code and data during execution of software applications. An application that is to be efficiently arranged in a software carrier medium is instrumented such that the status of whether a particular unit of code or data has been accessed during a time interval is recorded in a time-ordered bit sequence for each such unit. A sort routine is used to sort the order of time-ordered bit sequences within an array of such sequences. The sort routine invokes a comparison function that operates upon the temporal information stored in the two time-ordered bit sequences that are being compared for the routine. The order of the code and data in the software application is reordered in accordance with the results of the sort routine.

System and method for using data address sequences of a program in a software development tool

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Bellevue, WA, United States of America

Hoi Huu Vo