Skhynix Inc.

Hoe Seung Jung

Joo Young Lee

Dong Hoon Lee

Yun Chan Seo

Chi Heon Kim

Hye Mi Kang

Sung Kwan Hong

Chan Young Oh

According to embodiments of the present disclosure, if write operations for a memory block with efficient write operations according to a cache program mode and a memory block with a different property are mixed, the write operation is performed by switching the cache program mode to a normal program mode. Accordingly, it is possible to prevent or reduce performance degradation of the cache program mode due to a workload in which write operations of different property are mixed, thereby improving write operation efficiency.

Storage device, controller, and operating method of controller, capable of improving efficiency of program mode

A data storage device may include a storage and a controller. The storage a storage including a first region of a first physical address range and a second region of a second physical address range. The controller may generate map data including a plurality of map segments, a first segment entry and a second segment entry, and store, in the second region, the map data except for a first map segment. Each of the map segments includes a set of physical addresses corresponding to a plurality of sequential logical addresses. The first segment entry includes a first segment physical address associated with the first map segment and belonging to the first physical address range, and the second segment entry includes a second segment physical address associated with a second map segment and belonging to the second physical address range.

Data storage device and method of operating the same

A storage device may determine write throughput based on a plurality of write commands received from the outside of the storage device, and write target data write-requested from the outside to a first memory area including one or more of a plurality of first type memory blocks or a second memory area including one or more of a second type memory blocks according to whether the write throughput is greater than or equal to a threshold throughput. The first type memory blocks may operate at a higher speed than the second type memory blocks.

Storage device determining memory area to which data is written using write throughput and method of operation

A storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.

Storage device for loading map segment and sending map segment to external device, and operating method thereof

A memory system includes: a memory device including first memory blocks, within which a single bit is to be programmed into a memory cell by using a single level cell (SLC) method, and second memory blocks, within which two or more bits are to be programmed into a memory cell by using a multi-level cell (MLC)-or-more method, and a controller configured to program first data in the first memory blocks by using the SLC method and then migrate the first data from the first memory blocks into the second memory blocks by using the MLC-or-more method, wherein the controller is further configured to read the first or second memory blocks according to a number of free blocks included in the first memory blocks, when the read request for the second memory block is received after the specific amount of time.

Controller and memory system having the controller

In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.

Memory controller, memory system and operating method thereof

A data storage device includes a memory cell array comprising a plurality of pages each including K memory cells of which each stores N bits therein, where N and K are positive numbers greater than or equal to 2, wherein each of the pages stores one page data constituted by N subpage data each having K bits; a cache buffer receiving and caching N subpage data of first page data from a controller; and a page buffer sequentially buffering the respective cached N subpage data of the first page data and store the respective buffered N subpage data of the first page data in the memory cell array, wherein when a write operation for Msubpage data of the first page data is completed, the cache buffer receives and caches Msubpage data of second page data from the controller, where M is a positive number less than N.

Data storage device and operating method thereof

There are provided a memory system and an operating method thereof. The memory system includes: a memory device including a plurality of semiconductor memories; and a controller for generating a plurality of command queues respectively corresponding to the plurality of semiconductor memories by queuing a plurality of commands received from a host, and controlling the plurality of semiconductor memories to perform overall operations by outputting the plurality of commands queued in the plurality of command queues, wherein the controller holds a first command queue, among the plurality of command queues, corresponding to a first semiconductor memory, among the plurality of semiconductor memories, in which a program fail has occurred.

Memory system and operating method thereof

A data storage device includes a storage unit; and a controller configured to select a write mode by analyzing a tendency of commands received from a host device, and operate in the selected write mode to write data to the storage or to read data from the storage.

Data storage device for determining a write mode, operation method thereof and storage system having the same

A storage device includes a memory device including a memory cell array and a page buffer group coupled to the memory cell array, and a memory controller configured to store a plurality of cache data chunks to be sequentially programmed, and configured to input a next cache data chunk corresponding to a next program sequence to the page buffer group, when programming of Least Significant Bit (LSB) data of a cache data chunk among the plurality of cache data chunks is completed.

Storage device having improved cache performance and method of operating the same

A data storage device includes a nonvolatile memory device including a plurality of memory blocks each of which includes a plurality of pages; and a controller suitable for obtain block physical to logical (PL) data corresponding to a first memory block among the plurality of memory blocks, determine first and second target logical to physical (LP) pages, one or more first target LP segments stored in the first target LP page and one or more second target LP segments stored in the second target LP page, based on the block PL data and an LP segment position table, obtain the first target LP segments, and verify validity for one or more first PL data included in the block PL data, based on the first target LP segments, wherein the controller obtains the second target LP segments while verifying the validity for the first PL data.

A method for operating a data storage device includes storing an erase count corresponding to a physical address, as a reference value, in response to a first event; comparing a current value of the erase count with the reference value in response to a second event; and selectively performing a purge operation for the physical address, depending on a result of the comparing.

Growing community of inventors

Seoul, South Korea

Hoe Seung Jung