Skhynix Inc.

Hoe Sam Jeong

Jin Ho Seo

Min Kyu Kim

Kyoung Mook Lim

Jong Hyun Ra

Disclosed is an image sensor including a first sub-pixel array including a plurality of first pixel groups, which are respectively coupled to a plurality of first readout lines extending in a first direction and are adjacent to one another in a second direction intersecting the first direction; and a plurality of first switches suitable for selectively coupling a plurality of first floating diffusion nodes included in the plurality of first pixel groups, based on a plurality of first control signals.

Image sensor and operating method thereof

Disclosed is an image sensing device and an operating method thereof, the image sensing device including an image sensor suitable for generating first image signals, corresponding to some of a plurality of pixels, in a binning mode, and an image processor suitable for generating second image signals, corresponding to other pixels, by performing an interpolation operation based on the first image signals in the binning mode.

Image sensing device and operating method thereof

An image sensor for stably generating pulses of a precharge signal is disclosed. The image sensor includes a divider configured to generate a plurality of divided clock signals by dividing one or ore input clock signal, a precharge pulse generator configured to generate a first pulse signal by selecting any one of the plurality of divided clock signals in response to decoding signals of a first group, and generate a second pulse signal by selecting any one of the plurality of divided clock signals in response to decoding signals of a second group, and a precharge signal generator configured to generate a precharge signal by combining the first pulse signal and the second pulse signal.

Image sensor

A nonvolatile memory device includes a nonvolatile memory cell, a sensing circuit coupled between a sensing input line coupled to a bit line of the nonvolatile memory cell and a sensing output line, a sensing output grounding portion fixing an output signal of the sensing circuit at a low level if the output signal of the sensing circuit has a low level, and a bit line grounding portion fixing a bit line voltage at a ground voltage if the output signal of the sensing circuit is fixed at a low level.

Nonvolatile memory device for suppressing read disturbances

A nonvolatile memory device includes a nonvolatile memory cell and a variable resistive load portion. The variable resistive load portion is coupled between a bit line of the nonvolatile memory cell and a supply voltage line. The variable resistive load portion is suitable for changing a resistance value between the bit line and the supply voltage line according to a level of a supply voltage applied to the supply voltage line.

Nonvolatile memory devices having variable resistive load portion

A nonvolatile memory device includes a nonvolatile memory cell coupled to a bit line. The nonvolatile memory device may include a sensing circuit configured to output a sensing output signal for sensing a status of the nonvolatile memory cell based on a sensing input signal inputted to the sensing circuit through a sensing input line. The nonvolatile memory device may include a folding circuit coupled to the bit line to output the sensing input signal having a voltage low level or a voltage high level according to a voltage level of the bit line.

Folding circuit and nonvolatile memory devices

A nonvolatile memory device may include a nonvolatile memory cell and a sensing circuit. The sensing circuit is coupled to a bit line of the nonvolatile memory cell. The sensing circuit may be realized using an inverter comprised of a P-channel transistor coupled to a supply voltage line and an N-channel transistor coupled to a ground voltage. The gate of the P-channel transistor is coupled to the ground voltage.

Nonvolatile memory devices relating to operation ranges

A voltage supply device includes a bias generator, a control signal generator and a cell switching circuit. The bias generator divides a first supply voltage to output a plurality of divided supply voltages. The control signal generator receives the plurality of divided supply voltages to generate a plurality of control signals. The cell switching circuit receives the plurality of control signals to provide nonvolatile memory cells with one or more of a ground voltage, the first supply voltage, or a second supply voltage different from the first supply voltage. Each of the bias generator, the control signal generator and the cell switching circuit is implemented with medium voltage MOS transistors having a breakdown voltage of from approximately 7 volts to approximately 15 volts.

Growing community of inventors

Gyeonggi-do, South Korea

Hoe Sam Jeong