Samsung Electronics Co., Ltd.

Hoe-ju Chung

Kyu-Hyoun Kim

Tae-seong Jang

Il-Won Seo

Moo-Sung Chae

A semiconductor device having a plurality of output signals is provided. The semiconductor device includes a plurality of PMOS transistors each having a drain of connected to a predetermined node and a source supplied with a first power voltage. A plurality of first buffers are connected to the gates of the plurality of PMOS transistors. A plurality of NMOS transistors each have a drain connected to the predetermined node, and a source supplied with a first ground voltage. A plurality of second buffers are connected to gates of the plurality of NMOS transistors. The plurality of first buffers are supplied with the first ground voltage, the plurality of second buffers are supplied with the first power voltage, and a signal output from a previous portion of the semiconductor device is input into the first and second buffers at predetermined time intervals. As a result, skewing of the output signals is reduced.

Semiconductor device having a plurality of output signals

A delay time controlling circuit in a semiconductor memory device and method thereof for controlling a delay time preferably comprise a controller, a fuse unit having selectable fuse elements, a multiplexer, and a programmable variable delay circuit. With the multiplexer selecting the output of the controller, the controller generates a sequence of differing digital delay control signals to the programmable variable delay circuit in order to provide a plurality of unique delays in an output signal. When a desired time delay is monitored in the output signal, a programming signal is generated, which causes the specific digital control signal to be permanently programmed into the fuse unit via selective cutting of fuse elements. The multiplexer is then toggled via a selector fuse element to permanently select the output of the fuse unit as a control value source for the variable delay circuit.

Delay time controlling circuit and method for controlling delay time

A semiconductor capable of reducing skew between plural-bit output data by using a plurality of data output drivers and a method thereof. Each data output driver comprises a driver connected between an external power voltage and an external ground voltage, for pulling-up the output data in response to a first state of input data and for pulling-down the output data in response to a second state of the input data; a first delay circuit for varying transition delay time of the input data having the first state in response to signals received from other data output drivers; and a second delay circuit for varying transition delay time of the input data having the second state in response to signals received from other data output drivers.

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Suwon, South Korea

Hoe-ju Chung