Samsung Electronics Co., Ltd.

Hocheol Bang

Jieun Shin

Haewon Lee

Sang Kyu Kang

A semiconductor memory device includes a memory cell array including a plurality of memory cells and a control logic circuit configured to control the semiconductor memory device. The control logic circuit includes a mode register and a remaining lifetime calculating device configured to count usage metrics based on one or more of the following: a number of clock signals received from a memory controller, an amount of data transmitted or received to or from the memory controller, and/or a number of commands received from the memory controller. The remaining lifetime calculating device generates a remaining lifetime code representing a remaining lifetime of the semiconductor memory device based on the usage metrics, and stores the remaining lifetime code in the mode register.

Semiconductor memory device and memory system

A semiconductor memory device includes a mammy cell array including a plurality of memory cells and a control logic circuit configured to control the semiconductor memory device. The control logic circuit includes a mode register and a remaining lifetime calculating device configured to count usage metrics based on one or more of the following: a number of clock signals received from a memory controller, an amount of data transmitted or received to or from the memory controller, and/or a number of commands received from the memory controller. The remaining lifetime calculating device generates a remaining lifetime code representing a remaining lifetime of the semiconductor memory device based on the usage metrics, and stores the remaining lifetime code in the mode register.

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Hwaseong-si, South Korea

Hocheol Bang