Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Lsi Logic Corporation

Symbios Logic Inc.

Other

Symbios, Inc.

Hoang P Nguyen

John D Walker

Richard Thomas Schultz

Todd A Randazzo

Scott C Savage

Edson Wayne Porter

Andres R Teene

Maurice M Moll

Matthew Russell

Michael J McManus

Kenneth Stanley Szajda

Philip W Bullinger

Gerald R Haag

ZhiYuan Zou

A level shifter circuit configured for use between a core of a chip and input/output transistor of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.

CMOS level shifters using native devices

An ESD protection system that makes use of several different types of over-voltage protection devices provides ESD conduction paths between different power lines. For example, the system may employ shunt diodes between the ground lines of the different power supplies and between IC pads and power supply lines; SCR protection between IC pads and ground; and thick field device protection between different power supply V lines. In this way, a conduction path for an ESD event between two circuit elements may be implemented using the device whose switching characteristics are best suited to that application.

Electronic discharge protection system for mixed voltage application specific circuit design

The present invention provides for ESD protection while allowing the use of an input signal that is higher than V.sub.DD. The present invention preferably includes a protection device and a delay circuit coupled to an input pad and to a ground reference. The protection device is a preferred silicon controlled rectifier, and the delay circuit is preferably a low pass filter RC circuit that includes a resistor and a capacitor. A node associated with the delay circuit is coupled to circuitry of an integrated circuit. The circuitry has associated therewith at least one gate oxide breakdown voltage. A gate oxide breakdown voltage is prevented from being applied to the circuitry of the integrated circuit. When an ESD voltage is applied to the input pad, the voltage at that pad ramps or increases quickly. The delay circuit prevents the node from ramping as quickly by delaying the ramping or increasing of the node voltage. This delay provides time for the protection device to turn on and sink the ESD current.

ESD protection for high voltage level input for analog application

A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle. The method also preferably includes generating an enable pulse by generating a second clock signal in response to a first clock signal and combining the first and second clock signals to generate the enable signal, and generating a second data input signal in response to a first data input signal, where generating the second data input signal includes receiving an enable signal. The method preferably includes the step of generating an output signal in response to the second data input signal and the second clock signal, the output signal having a reduced metastable effect.

Meta-hardened flip-flop

An integrated circuit formed on a semiconductor substrate has a contact pad for communicating signals between an external device and an internal signal line. The pad is protected by an SCR that conducts electrostatic discharge pulses from the pad directly to a current sink. The SCR includes a subregion underneath a field oxide that has a field inplant that increases the dopant concentration. The field implant lowers the SCR trigger voltage, so that SCR triggers before an ESD pulse can cause latch-up or damage in other devices in the integrated circuit.

Field implant for silicon controlled rectifier

An ESD protection system that makes use of several different types of over-voltage protection devices provides ESD conduction paths between different power lines. For example, the system may employ shunt diodes between the ground lines of the different power supplies and between I/O pads and power supply lines; SCR protection between I/O pads and ground; and thick field device protection between different power supply V.sub.DD lines. In this way, a conduction path for an ESD event between two input, output power and ground pads may be implemented using the device whose switching characteristics are best suited to that application.

Electrostatic discharge protection system for mixed voltage application

In an electronic IC package, an I/O PAD circuit design which protects 3 Volt optimized I/O functional circuits from damage due to the application of external 5 Volt signals to the I/O PAD both while the functional circuit design is powered on and powered off. When the I/O circuits associated with the I/O PAD are powered on, the present invention protects the I/O circuits by applying well known designs. However, when the I/O circuits associated with the I/O PAD are powered off, the present invention draws power from the external 5 Volt signal to activate additional transistors to protect the powered off I/O circuits.

5-volt tolerant bi-directional i/o pad for 3-volt-optimized integrated

An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplexer. The multiplexer receives an input signal from the pad or a boundary scan signal from the core region and selectively provides one signal or the other to the core region.

Growing community of inventors

Fort Collins, CO, United States of America

Hoang P Nguyen