Hyundai Electronics Industries Co. Ltd.

Hoai Sig Kang

Dong Bum Koh

Hyun Eun Kim

Mun Weon Ahn

The present invention provides a CMOS (Complementary Metal Oxide Semiconductor) image sensor including a unit pixel, wherein the unit pixel includes photodiodes for receiving incident light and for generating photo charges, single sensing node for selectively receiving the photo charges outputted from the photodiodes; a reset transistor for resetting the single sensing node; and a drive transistor for outputting electrical signals corresponding to voltage levels of the single sensing node, and wherein the CMOS image sensor samples the electrical signals through the correlated double sampling and then outputs a final image value to an external device.

CMOS image sensor having common outputting transistors and method for driving the same

An MPEG decoder and an MPEG decoding method with two memory controllers is capable of separately controlling compressed data and decoded data. An MPEG decoder decodes a compressed input data formatted in an MPEG type. The MPEG decoder comprises a compressed data memory controller and a decoded data memory controller. The compressed data memory controller is coupled to a compressed data memory and controls the compressed data. The decoded data memory controller is coupled to a decoded data memory, and controls the decoded data. Since the compressed data flow and the decoded data flow are divided, the memory transfer rate is increased, and also the memory control is simple. In addition, the compressed data are able to be stored within the MPEG decoder. Therefore, the high-performance of the MPEG decoder and the high quality of the image are possible.

MPEG-decoder and MPEG decoding method with two memory controllers

An address translation unit for supporting multiple page modes, with each page mode having a different page size. The address translation unit includes a tag interface unit for outputting effective tag data in response to a page mode select signal, a tag memory for storing tag data and for comparing the effective tag data with previously stored tag data to generate a comparison signal in response to a word signal and a write control signal, a data interface unit for outputting effective physical data in response to the page mode select signal, a data memory for storing effective physical data from the data interface unit and for outputting a converted physical address in response to the word signal, the write control signal and the comparison signal, a decoder interface unit for receiving a part of a linear address in response to a page mode signal and for outputting the part of the linear address as an entry index signal, and a decoding unit for decoding the part of the linear address and outputting the word signal selecting an entry to the tag memory and the data memory in response to the entry index signal, the write control signal and a write way signal.

Address translation unit supporting variable page sizes

A bus arbitration apparatus includes N number of hierarchical arbitrators, wherein each hierarchical arbitrator contained in the lowest hierarchy is connected to p number of the bus request units. Especially the hierarchical arbitrator of each hierarchy has: a selector for generating a selection signal based on bus requests from the hierarchical arbitrators of a lower hierarchy and priorities of the hierarchical arbitrators of the lower hierarchy, wherein the selection signal represents a selected hierarchical arbitrator of the lower hierarchy, and for generating the bus request from the selected hierarchical arbitrator as a bus request from said each hierarchy; and a multiplexer, in response to the selection signal, for providing bus cycle information from the selected hierarchical arbitrator as bus cycle information of said each hierarchy.

Bus arbitrator with a hierarchical control structure

In a high performance microprocessor adopting a superscalar technique, necessarily using a cache memory, TLB, BTB and etc. and being implemented by 4-way set associative, there is provided an LRU memory capable of performing a pseudo replacement policy and supporting multi-port required for operating various blocks included in the microprocessor. The LRU memory comprises an address decoding block for decoding an INDEX.sub.-- ADDRESS to produce a READ.sub.-- WORD and a WRITE.sub.-- WORD in response to the first phase and a second phase of the CLOCK signal, respectively; an LRU storing block; a way hit decoding block for decoding a WAY.sub.-- HIT to produce a MODIFY CONTROL signal in response to the second phase of the CLOCK signal; a data modifying block for latching a READ.sub.-- DATA from the LRU storing block to produce a DETECTED DATA and modifying it in response to the MODIFY CONTROL signal so as to produce a WRITE.sub.-- DATA to the LRU storing block; and a write way decoding block for analyzing the DETECTED DATA so as to produce a WRITE.sub.-- WAY. This LRU memory reduces the load of superscalar microprocessor required for controlling the cache memory, TLB and BTB and simplifies an interface therebetween, so as to perform the LRU updating process in high speed, thereby improving the performance of the superscalar microprocessor.

High-performance LRU memory capable of supporting multiple ports

This invention is developed to provide a multi-port access memory having: a multi-port access memory cell block for storing data; a number of decoder for receiving an address for reading and writing the data and, in response to a read enable signal or a write enable signal, for decoding the address to thereby select one of word lines of the multi-port access memory cell block; and data selection circuit in response to the write enable signal, for relaying input data via a bidirectional data line to the multi-port access memory cell and, in response to the read enable signal, for receiving the data stored in the multi-port access memory cell to thereby provide the stored data.

Multi-port access memory employing a common read/write port

A translation lookaside buffer (TLB) for use of a microprocessor, using a content address memory (CAM), includes a block for generating a control clock for precharging a clock and an enable clock for driving data; a CAM block for comparing a linear address with stored data and generating hit signals representing whether or not its comparison result is a coincidence therebetween; a block for decoding the linear address applied from the outside, the linear address being for a distinction of respective entries; a hit signal generating block for outputting selection signals indicating where the hit signals inputted from the CAM block are generated; a block for storing a physical address; a block for selecting one out of the physical addresses outputted from each area of the storing block in response to the selection signal provided from the hit signal generating block; and a block for sensing a signal applied from the selection block.

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Kyoungki-do, South Korea

Hoai Sig Kang