Lovoltech, Incorporated

Qspeed Semiconductor Inc.

Ho Yuan Yu

Chong Ming Lin

Jay Denning

A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.

Programmable junction field effect transistor and method for programming same

An etched substrate structure is augmented by conductive material to provide enhanced electrical and/or thermal performance. A semiconductor device substrate comprising active regions defined on a top surface is masked and etched to define a pattern of blind features in a bottom surface of the substrate. A conductive material is then deposited on the surface of the blind features. The replacement of semiconductor material with the conductive material lowers the resistance between the active elements on the top surface and the bottom surface. The blind features may be placed in proximity to parasitic bipolar transistors in order to increase immunity to latchup. During wafer processing, a pattern of grooves aligned opposite to a scribe street pattern may be etched on the wafer back side in order to facilitate the separation of individual devices.

Structure and method for enhanced performance in semiconductor substrates

Programmable junction field effect transistor and method for programming the same

A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.

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Saratoga, CA, United States of America

Ho Yuan Yu