Samsung Electronics Co., Ltd.

Wisconsin Alumni Research Foundation

Snu Rdb Foundation

Ho-Young Song

Seong-Jin Jang

Hyun-Joong Kim

Sang-Uhn Cha

Hoi-ju Chung

Sang-Joon Hwang

Jong-Min Oh

Kwang-il Park

Kyo-Min Sohn

Cheol Su Kim

Dong-hyun Sohn

Young-Hyun Jun

Sung-Min Seo

Do-Yeon Kim

Chul-hee Yoo

Hyun-jin Kim

Nam Sung Kim

Chan-Kyung Kim

Jung Ho Ahn

Je-Min Ryu

Young-Hoon Son

Ju-yun Jung

Seong-Il O

Youn-sik Park

Sung-Hoon Kim

Seung-Jun Bae

Jong-Pil Son

Chang-Sik Yoo

Joung-Yeal Kim

Sang-Bo Lee

Gil-Su Kim

Je-Min Yu

Young-sam Park

Hoon Shin

Da-hye Kim

Man-ki Hong

Sang-Hoon Shin

Sang-woong Shin

Yong-Ho Cho

Byong-mo Moon

Chul-Soo Kim

Jong-sup Song

Hae-Suk Lee

Yun-Young Lee

Dong-Su Lee

Kwang-II Park

Han-Vit Jung

Seung-hwan Choi

Chi-Goo Kang

Sun-Woo Kim

A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Semiconductor memory devices, memory systems including the same and methods of operating memory systems

A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

Memory module, memory device, and processing device having a processor mode, and memory system

Provided are memory devices configured to perform row hammer handling operations, and memory systems including such memory devices. An example memory device may include a memory cell array including a plurality of memory cell rows; a row hammer handler that is configured to determine whether to perform a row hammer handling operation to refresh adjacent memory cell rows adjacent to a first row that is being intensively accessed from among the memory cell rows, resulting in a determination result; and a refresh manager configured to perform either a normal refresh operation for sequentially refreshing the memory cell rows or the row hammer handling operation, based on the determination result of the row hammer handler.

Memory devices performing refresh operations with row hammer handling and memory systems including such memory devices

A memory device a plurality of memory banks, a hammer address manager, and a refresh controller. The hammer address manager manages access addresses with respect to the plurality of memory banks and provides a hammer address for a hammer refresh operation among the access addresses, the hammer address being the access address that is accessed more than other access addresses. The refresh controller generates a hammer refresh address signal based on the hammer address, the hammer refresh address signal corresponding to a row that is physically adjacent to a row corresponding to the hammer address such that the row physically adjacent to the row corresponding to the hammer address is refreshed by the hammer refresh operation.

Refresh control circuit, memory device including the same and method of operating the same for hammer refresh operation

A packaged light emitting device can include a mounting substrate including first and second electrode portions that are separated by a recess defined by a first side surface of the first electrode portion and a second side surface of the second electrode portion that is opposite the first side surface. An insulation support member can partially fill a lower portion of the recess to partially cover the first side surface and partially cover the second side surface. A light emitting device can be coupled to the first and second electrode portions of the mounting substrate and a sealing member can be on the mounting substrate covering the light emitting device.

Packaged light emitting devices including electrode isolation structures and methods of forming packaged light emitting devices including the same

Provided are a quantum dot glass cell and a light-emitting device package including the quantum dot glass cell. The quantum dot glass cell may include a quantum dot powder in which quantum dots, inorganic homogenizing particles, and a binder are mixed, a dispersion matrix in which the quantum dot powder is dispersed, and a glass sealing structure surrounding the dispersion matrix. The quantum dot glass cell and the light-emitting device package including the quantum dot glass cell may have improved light emission characteristics and improved reliability.

Quantum dot glass cell and light-emitting device package including the same

Embedded refresh controllers included in memory devices and memory devices including the embedded refresh controllers are provided. The embedded refresh controllers may include a refresh counter and an address generator. The refresh counter may generate a counter refresh address signal in response to a counter refresh signal such that the counter refresh address signal may represent a sequentially changing address. The address generator may store information with respect to a hammer address that is accessed intensively and may generates a hammer refresh address signal in response to a hammer refresh signal such that the hammer refresh address signal may represent an address of a row that is physically adjacent to a row of the hammer address. Loss of cell data may be reduced and performance of the memory device may be enhanced by detecting the intensively-accessed hammer address and performing the refresh operation based on the detected hammer address efficiently.

Embedded refresh controllers and memory devices including the same

Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Device and method for repairing memory cell and memory system including the device

Provided are a light source package and a display device including the light source package. The light source package includes a substrate; a light-emitting device mounted on the substrate; a red phosphor layer formed adjacent to a surface of the light-emitting device; and an encapsulation layer for encapsulating the light-emitting device and the red phosphor layer, wherein a phosphor of the red phosphor layer is a fluoride-based red phosphor or a sulfide-based red phosphor. The light source package and the display device including the light source package display excellent color reproduction, without discoloration due to moisture after a long period of time.

Light source package and display device including the same

Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes: determining a weak row by counting an activated number of at least one row; requesting for refresh on the weak row based on a result of the determining; and performing target refresh on the weak row upon receiving a refresh command according to the requesting.

Memory device and memory system performing request-based refresh, and operating method of the memory device

Growing community of inventors

Hwaseong-si, South Korea

Ho-Young Song