Etron Technology, Inc.

Ho-Yin Chen

Chun Shiah

Shi-Huei Liu

Han-Nung Yeh

Han-Hsien Wang

Ting-Feng Chang

Yu-Hui Sung

Sen-Fu Hong

Cheng-Nan Chang

Hao-Jan Yang

Lien-Sheng Yang

Chih-Huei Hu

Kuo-Chen Lai

Hung-Jen Chang

Bo-Han Zhang

Wei-Jen Chen

Shu-Jen Wu

Tzu Jen Ting

Chun-Chia Chen

A memory includes a plurality of e-fuse sets, a sensing circuit, an Error-Correcting Code (ECC) circuit, and a plurality of registers. Each e-fuse set includes a plurality of e-fuses, and each e-fuse of the plurality of e-fuses corresponds to a first blown result. The sensing circuit senses the plurality of e-fuses to output a plurality of first blown results. The ECC circuit receives the plurality of first blown results and corrects a first blown result if the first blown result includes an error or directly outputs the first blown result if the first blown result comprises no error to generate a second blown result. The plurality of registers receive a plurality of second blown results. The plurality of second blown results adjusts predetermined settings of the memory, and a number of the plurality of registers is less than a number of the plurality of e-fuses.

Memory with electrically programmable fuse blown result correcting function and operational method thereof

An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.

Error correction method, error correction circuit and electronic device applying the same

A memory with an error correction function includes a controller and a memory cell array. The controller optionally writes written data to a normal storage area and a backup area of the memory cell array, and when the controller reads first data corresponding to the written data from the normal storage area, if at least two errors are included in the first data, the controller reads the backup area to output second data corresponding to the written data from the backup area.

Memory with an error correction function and related memory system

A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.

Circuit for outputting information of a memory circuit during a self-refresh mode and related method thereof

A method of operating a PSRAM includes selecting a bit on a word line of the PSRAM, keeping the word line on for a first predetermined duration after selecting the bit, writing a data into the bit in response to a write command, and keeping the word line on for a second predetermined duration after the write command ends.

Method of providing write recovery protection in PSRAM and related device

The latency of a PSRAM is set according to its current state when receiving an external command. If the PSRAM is not executing a specific operation or has completed the specific operation while meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a first latency. If the PSRAM is executing the specific operation or has completed the specific operation before meeting corresponding timing parameters, the PSRAM is configured to execute the external command with a second latency larger than the first latency.

Method of operating PSRAM and related memory device

A current mirror with immunity for the variation of threshold voltage includes raising the voltage difference between the gate and the source of a MOS in the current source, and increasing the channel length of the MOS for limiting the generated reference current.

Current mirror with immunity for the variation of threshold voltage and the generation method thereof

A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the word line. The second bi-directional tracking circuit is configured to track a second timing constraint associated with turning on the bit line, turning off the bit line, or accessing the cell via the bit line.

Memory device with bi-directional tracking of timing constraints

A plurality of refresh requests are generated at a predetermined period shorter than the longest time during which a PSRAM is able to retain a data without being refreshed. For two consecutive first and second refresh requests, the second refresh request is ignored if the interval between the first and the second refresh requests is not larger than a predetermined duration. The first refresh request is delayed if the first refresh request conflicts with an external command of the PSRAM.

Method of controlling a refresh operation of PSRAM and related device

A device for increasing chip testing efficiency includes a pattern generator, a reading unit, a logic operation circuit, and a judgment unit. The pattern generator is used for writing a logic voltage to each bank of a memory chip. The reading unit is used for reading logic voltages stored in all memory cells of each bank. The logic operation circuit is used for executing a first logic operation on the logic voltages stored in all memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank, and executing a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip. The judgment unit determines whether the memory chip passes the test according to the second logic operation result.

Device for increasing chip testing efficiency and method thereof

Method for detecting word line defect includes activating a first word line for reading a first data pre-stored in the memory cell, suspending the first word line for a predetermined period and then writing a second data complementary to the first data into the memory cell, activating again the first word line for reading a third data from the memory cell, and comparing the second and the third data for determining if an electrical coupling path exists between the first word line and a second word line.

Word line defect detecting device and method thereof

A memory module with failed memory cell repair function and method thereof are provided. The memory module comprises a programming interface, a mode register, a control signal generator, a fuse unit, a main memory array and a redundant memory array, wherein the programming interface is defined by selecting pins from a standard interface of the memory module. The programming interface is used to input a plurality of programming commands and a plurality of programming data. When the failed memory cells have occurred within the main memory array, the mode register will enter into a programming mode according to the programming commands, and the control signal generator will program the fuse unit, such that the redundant memory cells of the redundant memory array will be used to replace the failed memory cells. Thus, the fuse unit can be programmed directly through the standard interface, and the repairing period and the cost will be reduced efficiently.

Growing community of inventors

Hsinchu County, Taiwan

Ho-Yin Chen