Samsung Electronics Co., Ltd.

Ho-Yeon Jeon

Youn-Sik Choi

Jae-Gon Lee

Jin-Ook Song

Dae Hwan Kim

Young Hoon Lee

Min-joung Lee

Ah Chan Kim

Min Joung Lee

Mun Won Lee

A system-on-chip is provided. The SoC includes a system power supply circuit which outputs a first supply voltage, an intellectual property (IP) which receives the first supply voltage and operates at a second supply voltage, a supplemental power supply circuit which generates a supplemental voltage; and a comparator which compares the first supply voltage with the second supply voltage and outputs a comparison signal, wherein the supplemental voltage is provided to the IP based on the comparison signal.

System on chip including a supplemental power supply circuit

A semiconductor device and a power-off method of the semiconductor device, the semiconductor device including a first power source group including first and second power sources, a second power source group including a third power source and a power sequence controller. The power sequence controller performs power-on operations and power-off operations of the first to third power sources. The power sequence controller starts a power-off operation of the first power source group at a first time, and starts a power-off operation of the second power source group when the power voltage of the first power source group becomes a first voltage or when a first reference time has passed from the first time.

Semiconductor device and power off method of a semiconductor device

In one embodiment, the clock management circuitry includes a first master clock controller configured to provide a first command to a first slave clock controller via a first channel based on a received first clock request. The clock management circuitry also includes the first slave clock controller configured to control outputting a first clock signal based on the first command.

System on chip including clock management unit and method of operating the system on chip

A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.

System-on-chip to support full handshake and mobile device having the same

A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.

Semiconductor device and method for profiling events in semiconductor device

A system on chip (SoC) includes a plurality of function circuits including a plurality of logic circuits and a plurality of function circuits each of which includes a logic circuit and a memory, and a plurality of power path controllers respectively coupled to a plurality of first power sources at first input terminals, commonly coupled to a second power source at second input terminals, and respectively coupled to the memories at output terminals. The logic circuits are respectively coupled to the first power sources, and configured to be supplied with a plurality of first power supply voltages from the first power sources, respectively. Each of the memories is configured to be selectively supplied, by a corresponding one of the power path controllers, with one of a corresponding one of the first power supply voltages from a corresponding one of the first power sources and a second power supply voltage from the second power source.

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Hwaseong-si, South Korea

Ho-Yeon Jeon