Hynix Semiconductor Inc.

Skhynix Inc.

Ho Uk Song

A Ram Rim

Jun Hyun Chun

Young Suk Seo

Tae Jin Kang

Kyoung Youn Lee

Hyun Seung Kim

Shin Ho Chu

Duck Hwa Hong

Joo Hyeon Lee

Tae Kyun Shin

Mi Hyun Hwang

Min Jun Choi

An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

Electronic device for adjusting refresh operation period

A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, an enablement moment of the first power control signal controlled according to a logic level combination of temperature code signals in response to a mode signal. The sense amplifier circuit may generate a first power signal driven in response to the first power control signal and may generate a second power signal driven in response to a second power control signal. The sense amplifier circuit may sense and amplify a level of a bit line using the first power signal and the second power signal.

Semiconductor systems for fast sensing speed and correct amplification

A semiconductor device may be provided. The semiconductor device may include a reference mat including a reference bit line and a reference word line, the reference mat, located adjacent to a normal mat, and the reference mat configured such that a capacitance of the reference bit line is adjusted based on a signal of the reference word line. The semiconductor device may include a drive controller configured to drive the signal of the reference word line with a drive voltage based on a boosting voltage, the drive voltage having a lower voltage level than the boosting voltage.

Semiconductor device

Semiconductor systems for fast sensing speed and correct amplification operation

An apparatus for adjusting an internal voltage includes a device characteristic detection circuit which detects a device characteristic, compares the device characteristic with an external clock, and generates a comparison signal, and an internal voltage adjustment circuit which receives an adjustment code generated based on the comparison signal, adjusts a level of an internal voltage, and generates a level-adjusted internal voltage.

Apparatus and system for adjusting internal voltage

An internal voltage generation circuit may include a temperature information generation unit configured to generate a temperature code having a code value corresponding to a temperature. The temperature information generation unit may include a process variation information generation unit configured to generate a process code having a code value corresponding to a process variation. The temperature information generation unit may include a code combination unit configured to generate a combination code in response to a ratio control signal, the temperature code, and the process code. The temperature information generation unit may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of the combination code.

Internal voltage generating circuit for generating internal voltage according to temperature and process variation

An output apparatus includes an output driving unit configured to drive a final output signal; an output compensating signal generation unit configured to generate a delayed output signal by delaying the output signal by a predetermined time, and generate an output compensating signal based on the delayed output signal and the output signal; and an output driving compensation unit configured to compensate for the final output signal to a level opposite to a level to which the final output signal is driven.

Output apparatus and output system including the same

A semiconductor memory device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal, the first power control signal having an enablement period that may be controlled in response to a temperature signal having a cycle time. The cycle time may be controlled according to a mode signal and an internal temperature. The sense amplifier circuit may generate a first power signal driven to have a first drive voltage in response to the first power control signal. In addition, the sense amplifier circuit may sense and amplify a level of a bit line using the first power signal as a power supply voltage.

Semiconductor devices and semiconductor systems including the same

A semiconductor apparatus includes: an output timing controller configured to delay an applied external read command by a predetermined time and generate a normal output enable flag signal, during a normal mode, a test output timing controller configured to generate a DLL clock signal from an external clock signal, delay the applied external read command in synchronization with the DLL clock signal, and output the delayed applied external read command as a test output enable flag signal, during a test mode, and a multiplexer (MUX) configured to output any one of the normal output enable flag signal or the test output enable flag signal as an output enable flag signal.

Semiconductor apparatus

A semiconductor device and method of operation having reduced read time of fuse array information during boot-up operation. When fuse array information is read, only repaired fuse-set information is read such that a read time of the semiconductor memory device is reduced, resulting in an increased read margin.

Semiconductor device and method of operation

A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.

Semiconductor memory device with a skew signal generator for adjusting a delay interval of internal circuitry

An internal voltage generation circuit includes a first enable signal generator configured to delay an active signal to generate a first enable signal, a comparison signal generator configured to compare the internal voltage with an internal reference voltage to generate a comparison signal, a pulse signal generator configured to receive the first enable signal and to generate a pulse signal, a transmission device configured to buffer and transfer the comparison signal as a pull-down signal, and a drive device configured to drive the driving signal to the first level in response to the pull-down signal.

Internal voltage generation circuit

Semiconductor memory device having a skew signal generator for adjusting a delay interval of internal circuitry

A temperature data output circuit is provided which is capable of outputting a temperature signal which is enabled when an internal temperature of at least one of the semiconductor memory chips mounted on a multi chip package exceeds a predetermined temperature.

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Icheon-si, South Korea

Ho Uk Song