Skhynix Inc.

Hynix Semiconductor Inc.

Ho Seok Em

Seok Joon Kang

Chang Yong Ahn

Jin Su Park

Dong Keun Kim

Min Chul Shin

Taek Seung Kim

An operating method of a nonvolatile memory apparatus includes determining a first threshold voltage of a memory cell by using a first read voltage. The method includes determining a second threshold voltage of the memory cell by using a second read voltage having a different voltage level from the first read voltage based on write data and the first threshold voltage of the memory cell. The method includes writing the write data into the memory cell based on the first and second threshold voltages of the memory cell.

Nonvolatile memory apparatus, write method of the nonvolatile memory apparatus, and system using the nonvolatile memory apparatus

A non-volatile memory apparatus includes a memory cell coupled between a global bit line and a global word line. A bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal. A snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell. A word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and may increase an amount of a current flowing through the memory cell based on the current enable signal.

Nonvolatile memory apparatus for mitigating snap-back disturbance, and read and write method of the nonvolatile memory apparatus

A semiconductor system may include a memory controller and a non-volatile memory apparatus. The memory controller may generate a recovery command signal by measuring a power off time of the non-volatile memory apparatus. The non-volatile memory apparatus may perform a drift recovery operation based on the recovery command signal.

Nonvolatile memory apparatus, semiconductor system including the nonvolatile memory apparatus, and operating method of the nonvolatile memory apparatus

A test circuit block may include a first signal line, a second signal line, a high resistive path unit, and a low resistive path unit. The high resistive path unit may be connected between the first signal line and the second signal line. The low resistive path unit may have a resistance lower than that of the high resistive path unit. The low resistive path unit may be selectively connected in parallel with the high resistive path unit between the first signal line and the second signal line.

Test circuit block, variable resistance memory device including the same, and method of forming the variable resistance memory device

A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. A voltage clamping circuit configured to limit a voltage level of the global bit line.

Non-volatile memory apparatus including voltage clamping circuit

A semiconductor memory apparatus includes a bias voltage generation circuit configured to generate a bias voltage according to a read voltage or a write voltage in response to a read signal and a write signal, a data discrimination circuit configured to generate a set enable signal and a reset enable signal in response to data and the write signal. The semiconductor memory apparatus also includes a current selection circuit configured to generate a first current in response to the read signal, the set enable signal, and the reset enable signal. The semiconductor memory apparatus further includes a driver configured to receive the first current and generate a second current in response to a voltage level of the bias voltage, and a first switch configured to provide the second current to a memory cell in response to the read signal and the write signal.

Resistive memory apparatus with a single read/write driver

A semiconductor memory apparatus may include a memory cell, a write driver, and a voltage adjustment circuit. The write driver may provide the memory cell with a program current based on a write data. The voltage adjustment circuit may adjust a voltage level of a global word line coupled to the memory cell when a current flowing through the memory cell or the voltage level of the global word line is greater than a threshold value.

Semiconductor memory apparatus for adjusting voltage level of global word line, and operating method thereof

A resistive memory device and a method may be provided. The resistive memory device may include a reset voltage-detecting circuit, a set voltage-detecting circuit, a control circuit and a read voltage-generating circuit. The reset voltage-detecting circuit may receive a variable preliminary reset current to detect reference reset voltage information. The set voltage-detecting circuit may receive a variable preliminary set current to detect reference set voltage information. The control circuit may receive the reference reset voltage information and the reference set voltage information to determine middle voltage information of the reference reset voltage information and the reference set voltage information. The read voltage-generating circuit may receive the middle voltage information to generate a read voltage.

Resistive memory device and method relating to a read voltage in accordance with variable situations

A current driver may include a current applying circuit and a current adjusting circuit. The current applying circuit may include a threshold switching element, and may provide unlimited amount of current while occupying small circuit area therefor. The current adjusting circuit may provide a bias voltage and control an amount of the current provided from the current applying circuit.

Current driver, write driver, and semiconductor memory apparatus using the same

A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal as soon as the comparison flag signal is enabled.

Semiconductor memory apparatus

A semiconductor memory apparatus may include a write driver, a data sensing section, and a programming control section. The write driver may write an input data into a memory cell in response to a write signal. The data sensing section may generate a comparison flag signal by comparing an output data outputted from the memory cell with a reference voltage in response to a verification read signal. The programming control section may generate the write signal for an initial write operation and the verification read signal in response to a write command, and generate the write signal for a following write operation as soon as the comparison flag signal is at a predetermined level.

A method for measuring a write current of a semiconductor memory device includes the steps of: programming initial data into memory cells which are to be programmed substantially at the same time; determining whether the memory cells are programmed into the same state or not; inputting test data when the memory cells are programmed into the same state; setting write current paths of the memory cells by comparing the initial data and the test data; and measuring a write current consumed when the test data are programmed into the memory cells.

Semiconductor memory device capable of measuring write current and method for measuring write current

A variable resistance memory device includes memory cells arranged at a region where word lines and bit lines cross each other, control logic configured to generate a command flag indicative of a program operation mode in response to a program command provided from an external device and configured to control the program operation of the memory cells based on the command flag and a write driver configured to be activated in response to the flag command and configured to supply a program current to the memory cells.

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Hwaseong-si, South Korea

Ho Seok Em