Samsung Electronics Co., Ltd.

Ho-Ouk Lee

Se-Min Jung

Hyo-dong Ban

According to some embodiments, a method includes forming at least two contact plugs that penetrate an insulating layer to connect with a semiconductor substrate. The contact plugs have an upper surface and upper sidewalls that are higher than a top surface of the insulating layer. An etch stop covers the contact plugs and the insulating layer, and a molding layer is formed over the etch stop layer. The molding layer is etched to form a molding pattern having an opening. A bottom of the opening includes a central region that exposes the etch stop on the upper surface and a peripheral region that extends from the central region and the etch stop layer. The etch stop is etched to expose the upper surface. Storage electrodes are formed to contact the contact plugs. The molding pattern is removed to expose the storage electrodes. Other embodiments are described and claimed.

Method of fabricating semiconductor device by exposing upper sidewalls of contact plug to form charge storage electrode

Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern including a gate electrode and a gate capping layer pattern is formed in the peripheral circuit region, the gate capping layer pattern and the word line capping layer pattern having different etching selectivity ratios. A pad interlayer insulating layer and a bit line interlayer insulating layer having approximately the same etching selectivity ratio as the gate capping layer pattern are sequentially formed over a surface of the semiconductor substrate having the gate spacers.

Growing community of inventors

Gyeonggi-do, South Korea

Ho-Ouk Lee