Lsi Corporation

Lsi Logic Corporation

Ho-Ming Leung

Elliot N Linzer

Elliot Sowadsky

Gary Chang

Suryanaryana M Potharaju

Fan Zhang

Peter G Panagas

Wern-Yan Koe

Eric Hung

Kasturiranga Rangam

Chiu-Tsun Chu

Lowell Leroy Winger

Aaron G Wells

Hidetaka Magoshi

Simon Booth

Nasima Parveen

Remi C Lenoir

Timothy J Wilson

Ka-Shu Ko

Venkatesh Balasubramanian

Soo-Chul Han

Zoltan Toth

Omer F Orberk

Daniel S Perrin

An apparatus including a processor and a memory. The processor may be configured to process pixel data comprising eight or more bits. For pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of the pixel are packed with LSBs from one or more other pixels into a second byte. The memory may be coupled to the processor and configured to store the first byte in response to a first pointer and the second byte in response to a second pointer. The first byte and the second byte are stored independently in the memory.

Hybrid multiple bit-depth video processing architecture

A method for transitioning a video system is disclosed. The method generally includes a first step for (A) executing in a processing circuit a standby code stored in a nonvolatile memory while the video system is in an off state, the off state defining a low power configuration for the processing circuit and a power off condition for the video system, the standby code being responsive to a plurality of wake up conditions to wake up the video system. In a second step, the method may (B) store an application code in a volatile memory while in the off state, the application code configured to operate the video system while in an on state of the video system. The method generally includes a third step for (C) transitioning from the off state to the on state upon detection of at least one of the wake up conditions. A step for (D) executing in the processing circuit the application code while in the on state to decode video may also exist in the method.

DVD recorder and PVR instant on architecture

A method for determining a first and a second reference picture used for inter-prediction of a macroblock, comprising the steps of (A) finding a co-located picture and block, (B) determining a reference index, (C) mapping the reference index to a lowest valued reference index in a current reference list and (D) using the reference index to determine the second reference picture.

Method and apparatus for determining a second picture for temporal direct-mode block prediction

A method for processing a compressed signal of digital video is disclosed. The method generally includes the steps of (A) generating a decompressed signal by decompressing the compressed signal of digital video, (B) generating a filtered signal by spatial filtering the decompressed signal, wherein the spatial filtering is arranged to reduce mosquito noise within the decompressed signal and (C) generating a video signal by adding synchronization information to the filtered signal, the synchronization information being suitable for synchronizing a video display to the filtered signal.

Mosquito noise reduction filter in digital decoders

An apparatus comprising a video decoder, a video memory and a global motion circuit. The video decoder may be configured to generate a decoded video signal in response to a coded video signal. The video memory may be connected to the video decoder. The global motion circuit may be configured within the video decoder circuit. The global motion circuit may be configured to (i) receive one or more warp points and (ii) generate one or more warping addresses presented directly to the video memory.

Method and/or apparatus for implementing global motion compensation in a video system

An apparatus comprising a buffer circuit, a rotation circuit and a memory. The buffer may be configured to store original image data in one or more sub-matrices. The rotation circuit may be configured to (i) produce rotated data and (ii) store the rotated data in a transposed matrix. The memory may be configured to position the rotated data in the transposed matrix. The transposed matrix comprises final image data rotated by a predetermined angle from the original image data.

Efficient and high speed 2D data transpose engine for SOC application

An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Method and/or apparatus for video data storage

An apparatus comprising an oscillator circuit, a control circuit, a counter circuit and a detector circuit. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to a first error signal and a second error signal. The counter circuit may be configured to generate the first error signal in response to the output signal and an input signal. The detector circuit may be configured to generate the second error signal in response to the output signal and the input signal.

Low jitter and/or fast lock-in clock recovery circuit

A method for motion estimating. The method generally includes the steps of (A) generating a first interpolated block having a sub-pixel resolution in response to a first interpolation process operating on a reference block of a reference frame of a video signal having an integer pixel resolution, (B) generating a motion vector in response to the first interpolated block and a current block of a current frame of the video signal having the integer pixel resolution and (C) generating a second interpolated block having the sub-pixel resolution in response to a second interpolation process operating on the reference block.

Motion estimation engine with parallel interpolation and search hardware

One aspect of the present invention concerns a method for controlling the frequency of oscillation of a local clock signal comprising the steps of (A) generating the clock signal in response to a first control signal, (B) generating the first control signal in response to one of a plurality of adjustment signals selected in response to a second control signal and (C) generating the second control signal in response to a comparison between a local timestamp and an external timestamp.

Integrated circuit with on-chip clock frequency matching to upstream head end equipment

An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.

Real time clock architecture and/or method for a system on a chip (SOC) application

An apparatus comprising a phase lock loop circuit and a control circuit. The phase lock loop circuit configured to generate an output signal having a first frequency in response to (i) an input signal having a second frequency, (ii) a first divider value and (iii) a second divider value. The second divider value may control spread spectrum modulation of the phase lock loop circuit. The control circuit configured to generate the second divider value in response to (i) the output signal and (ii) a programmable control signal.

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Cupertino, CA, United States of America

Ho-Ming Leung