Hong Kong Applied Science and Technology Research Institute Company, Limited

Ho Ming (Karen) Wan

Kwai Chi Chan

Yat To (William) Wong

Kwok Kuen (David) Kwong

Kam Chuen Wan

Chun Fai Wong

Tin Ho (Andy) Wu

Andrea Baschirotto

Leung Ling (Alan) Pun

Hok Mo Yau

Guangjie Cai

Tai Yin Wong

Guang Jie Cai

Sze Wing Leung

A bio-sensing processor chip acts as an auto-configurable platform to support a wide variety of bio-sensors. Nano-wires with attached bio-receptors for specific bio-molecules, ECG, and SPO2 bio-sensors drive analog voltages or currents to analog inputs of the bio-sensing processor chip. These analog inputs are divided into three sections. An input sensor detector/decoder detects which analog inputs are active and configures an analog-to-digital converter (ADC) to convert first-section inputs to 12 digital bits, second-section inputs to 16 bits, and third-section inputs to 20 bits. An Analog Front-End (AFE) is bypassed for the first section inputs but amplifies and filters second and third section inputs. A Universal Asynchronous Receiver Transmitter (UART) sends the converted digital values to a nearby external device using NFC or WiFi transmitters. When no battery is detected, energy is harvested from NFC signals from the external device, and one-shot measurements are made.

Self-powered and battery-assisted CMOS wireless bio-sensing IC platform

A low-headroom current driver does not use an op amp or resistor. A sensing transistor having its source connected to a drain of an output transistor senses variations in an output current. The gate, source, and drain voltages of the sensing transistor are mirrored to a sense mirror transistor to control a sense current. The sense current is mirrored to a reference source transistor to generate a mirrored sense current. An error between the mirrored sense current and a fixed reference current is stored as charge on an error-storing capacitor. The stored error charge creates a negative-feedback compensation current that adjusts a gate voltage generated by a feedback-driving transistor. The adjusted gate voltage controls the gate of the output transistor to compensate for the sensed variation in output current. The sensing current is also compensated using a sense-mirror tail transistor connected to the sense mirror transistor.

Low-headroom constant current source for high-current applications

A correcting asynchronous Successive-Approximation Register (SAR) analog-to-digital converter (ADC) detects and corrects metastability errors. An analog signal is synchronously sampled by a system clock, but data bits are converted asynchronously. A valid detector compares true and complement outputs of a comparator that compares the sampled voltage to a DAC voltage generated from digital test value from the SAR. Once the true and complement outputs diverge past logic thresholds, the valid detector activates a VALID signal indicating that comparison is completed. The compare result is then latched in as a data bit and the SAR advances to the next test value. Once all bits have been converted, an End-of-Conversion (EOC) is signaled. If the EOC does not occur by the end of the system clock, a metastability error is detected. The current bit that never finished comparison is forced high and all other unconverted bits are forced low.

Asynchronous successive-approximation-register analog-to-digital converter (SAR ADC) in synchronized system

A Programmable-Gain Amplifier (PGA) has a digital value that programmably adjusts the gain of the analog amplifier. A variable capacitor has several switched sub-capacitors that are enabled by the digital value. Enabled sub-capacitors are switched between a sampled input and a virtual ground on one terminal, and connect to a summing node on the other terminal. The summing node connects to the inverting input of an op amp either through a switch or through a double-sampling capacitor that stores an offset. A feedback capacitor is in parallel with a sampling capacitor during a second clock phase when direct-charge transfer occurs, reducing power consumption of the amplifier. The feedback capacitor samples the sampled input during the first clock phase. The PGA gain is proportional to the sum of capacitances of enabled sub-capacitors. The gain can be adjusted for sensor inputs to an Analog Front-End (AFE), such as for an electro-cardiogram (ECG).

Digitally-programmable gain amplifier with direct-charge transfer and offset cancellation

A bridge rectifier operates on low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a transistor bridge across the A.C. inputs to produce an internal power voltage. Another four diode-connected transistors form a start-up diode bridge that generates a comparator power voltage and a reference ground. The start-up diode bridge operates even during initial start-up before the comparator and boost drivers operate. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors in the transistor bridge with voltages boosted higher than the peak A.C. voltage. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow.

Diode-less full-wave rectifier for low-power on-chip AC-DC conversion

An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.

Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge

A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.

Configurable cascading sigma delta analog-to digital converter (ADC) for adjusting power and performance

A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.

Charge compensation calibration for high resolution data converter

A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.

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Hong Kong, China

Ho Ming (Karen) Wan