Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Ho-Kyoon Kwon

Byoung-Sun Na

Won-hee Lee

Ji-Hyun Kwon

Jong-Woong Chang

Hye-Seok Na

Shin-Tack Kang

Ju-Hee Lee

Gwang-Bum Ko

Dong-Gyu Kim

Soon-Il Ahn

Dae-Ho Song

Dong-Hyon Ki

Kee-Byem Kim

Yun-Soo Kim

Hoon Bae Kim

Joon-Chul Goh

Sung-Man Kim

Kwang-chul Jung

Seung-Soo Baek

Bong-Hyun You

Bon-Yong Koo

Sun-kyu Joo

Jeong Min Park

Dong-Hyeon Ki

Sang-Jin Jeon

Hee-wook Do

Myoung-Soo Kim

Hye-ran You

Seung-hoo Yoo

Dong-Yoon Lee

Sung-Min Kang

Yun Hee Kwak

Sang-Ik Lee

Hyun-cheol Moon

Kyoung-Ho Lim

Ki-Seok Cha

Jun-Ki Jeong

Embodiments of the present disclosure provide a thin-film transistor (TFT) panel structured to prevent the deterioration of image quality due to the luminance change of backlight. According to an embodiment, the TFT panel includes: an insulating substrate; a first gate line and a first data line which are formed on the insulating substrate to be insulated from each other and cross each other; a first subpixel electrode which is formed on the insulating substrate and connected to the first gate line and the first data line by a first TFT; a second subpixel electrode which is formed on the insulating substrate and separated from the first subpixel electrode; a connecting electrode which is directly connected to any one of the first and second subpixel electrodes and capacitively coupled to the other one of the first and second subpixel electrodes; a semiconductor pattern which is formed between the connecting electrode and the insulating substrate; and a light-shielding pattern which is formed between the semiconductor pattern and the insulating substrate, is overlapped by the connecting electrode, and blocks light.

Thin-film transistor panel

A method of repairing a short of a pixel electrode and a storage electrode including irradiating laser to separate a portion shorted to the pixel electrode among the storage electrode to be disconnected, in which the storage electrode includes a first portion overlapping a data line between two adjacent gate lines and a second portion connected to the first portion and enclosing an edge of a pixel area except for a region where the first portion is formed, the pixel area is defined by the data line and a gate line, a thin film transistor is coupled to the data line, the gate line, and the pixel electrode, and two adjacent pixel areas are defined by the two adjacent gate lines and two adjacent data lines, and the storage electrode is branched between pixel electrodes respectively formed in the two adjacent pixel areas.

Thin film transistor array panel, liquid crystal display, and method to repair the same

A method to repair a data line in a thin film transistor array panel includes, if the data line is disconnected at a disconnection portion, irradiating a laser on at least one side of the disconnected portion of the data line to short the data line and a storage electrode, and irradiating the laser to separate a portion shorted to the data line among the storage electrode to be disconnected. The storage electrode includes a first portion overlapping the data line between two adjacent gate lines and a second portion connected to the first portion and enclosing an edge of a pixel area except for a region where the first portion is formed. Two adjacent pixel areas are defined by the two adjacent gate lines and two adjacent data lines, and the storage electrode is branched between pixel electrodes.

A display apparatus includes a plurality of pixels arranged in columns and rows in a display area, a data line extending in a first direction and connected with pixels of a k-th column ('k' is a natural number) and a (k+1)-th column, a gate line extending in a second direction crossing the first direction and connected with ones of the pixels, a gate signal line extending in the first direction and connected with the gate line, and a gate driver in a first peripheral area adjacent to a first longer side of the display area and having a first width, and configured to apply a gate signal to the gate line.

Display apparatus

In the display apparatus, a gate driver receives at least one clock to sequentially provide gate lines in a display panel with a gate signal in a high state corresponding to a high interval of the clock. The gate driver includes a plurality of amorphous silicon transistors and is formed in the display panel through a thin film process. The clock has a delay time of about 2.0 &#x3bc;s or less. If the delay time of the clock is reduced less than about 2.0 &#x3bc;s, a threshold voltage margin of the transistors increases, so that the gate driver may not malfunction in a high temperature aging process. As a result, the gate driver may be prevented from malfunctioning in the high temperature aging process.

Display apparatus and method thereof

A display device includes a plurality of pixels arranged in a column direction and in a row direction, as well as a data line connected to a pixel of a k-th column (where 'k' is a natural number) and a (k+1)-th column in an odd-numbered row of the pixels, and connected to a pixel of a (k&#x2212;1)-th column and a (k+2)-th column in an even-numbered row of the pixels. A data driving part is configured to apply a data signal to the data lines.

Display device having higher aperture ratio and lower power consumption

A method of driving a gate line includes: charging one of a scan start signal and a carry signal provided from a previous stage to a first node of a present stage; outputting a gate signal through a gate node of the present stage by pulling up a high level of a first clock signal at the first node to boost up a voltage potential of the first node; discharging the voltage potential of the first node and a voltage potential of the gate node to hold the first node and the gate node at a first power voltage as the first clock signal is shifted to a low level; and receiving a voltage potential signal of a second node of the previous stage, the second node holding a gate signal outputted from the previous stage, to reduce a ripple generated at the first node.

Method of driving a gate line, gate drive circuit and display apparatus having the gate drive circuit

The present invention relates to a thin film transistor array panel, a liquid crystal display, and a method capable of reducing an effect on neighboring pixels in a process of repairing a pixel defect. The thin film transistor array panel may include: a thin film transistor connected to a gate line and a data line to define a pixel area; a pixel electrode formed in the pixel area and connected to the thin film transistor; and a storage electrode including a first portion overlapping the data line between two adjacent gate lines. The storage electrode may also include a second portion connected to the first portion and enclosing an edge of the pixel area except for a region where the first portion is formed. The storage electrode may be branched between pixel electrodes respectively formed in two adjacent pixel areas.

A touch display substrate includes a first data line, a first gate line, a first pixel electrode, a second gate line, a second pixel electrode, a sensor data line and a first sensor electrode. The first data line extends along a first direction. The first gate line extends along a second direction. The first pixel electrode is electrically connected to the first data line and the first gate line. The second gate line is substantially parallel with the first gate line. The second pixel electrode is adjacent to the first pixel electrode and electrically connected to the first data line and the second gate line. The sensor data line is adjacent to the second pixel electrode and substantially parallel to the first data line. The first sensor electrode is electrically connected to the sensor data line.

Touch display substrate and touch display panel having the same

A gate driver that comprises n shift registers, wherein n is an integer equal to or larger than 1, each of the n shift registers includes; a start stage which outputs a gate signal and starts its operation in response to a start signal, and a plurality of subsequent stages which are connected to each other in sequence, and which sequentially output a plurality of gate signals in response to a signal output from the start stage, wherein at least one stage of the plurality of subsequent stages is reset by the start signal.

Gate driver and display apparatus having the same

A thin film transistor array panel includes a gate line and the driver connection line formed with the same layer material, a data line and a driving pad formed with the same layer material, a first field generating electrode and a connecting member formed with the same layer material, and a second field generating electrode and a dummy electrode layer formed with the same layer material.

Thin film transistor array panel

A display substrate includes a gate line extended in one direction of a base substrate, a first data line extended in a direction crossing the gate line, a transverse storage line extended in the extending direction of the gate line and crossing the first data line, a longitudinal storage line extended in the extending direction of the first data line and crossing the transverse storage line, a portion of an overlapping area between the longitudinal storage line and the transverse storage line is exposed in a contact part region having an opening partially exposing the transverse storage line. A contact electrode covers the contact part opening and makes electrical contact with each of the transverse storage line and the longitudinal storage line.

Display substrate

A substrate includes a storage line, first and second gate lines and first and second pixel electrodes. The storage line extends along a first direction on the substrate. The first and second gate lines are substantially parallel with the storage line. The first pixel electrode is formed between the first gate line and the storage line. The second pixel electrode is formed between the second gate line and the storage line.

Array substrate, a display panel having the array substrate and a method of manufacturing the array substrate

In a display apparatus, pixels are arranged in a matrix defined by gate lines and data lines, and each pixel includes a first sub pixel charged to a first pixel voltage and a second sub pixel charged to a second pixel voltage having a same voltage level as the first pixel voltage. A voltage controller controls a voltage level of the first and second pixel voltages charged in the pixels corresponding to the first through penultimate pixel rows in response to a next gate signal. A dummy voltage controller controls a voltage level of the first and second pixel voltages charged in the pixels corresponding to the last pixel row in response to a dummy gate signal. Where a dummy voltage controller is not included, a black matrix partially covers the efficient display area of the pixels corresponding to the last pixel row.

Growing community of inventors

Seoul, South Korea

Ho-Kyoon Kwon