Samsung Electronics Co., Ltd.

Ho-Ki Lee

Sang-Woo Lee

Gil-heyun Choi

Jin-ho Park

Hyun-Su Kim

Eun-Ok Lee

Kwang-Jin Moon

Sung-Tae Kim

Kyu-Hee Han

Gilheyun Choi

Kwang-jin Moon

Jun-ho Park

Kyoung-Hee Kim

Jongwon Hong

Gwang-Hyun Baek

Ki-Jeong Kim

Du-Chul Oh

Jin-Kwan Lee

A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines.

Semiconductor devices

A semiconductor memory device includes conductive patterns vertically stacked on the substrate and having pad regions extended further at edge portions of the conductive patterns as the conductive patterns descend from an uppermost conductive pattern to a lowermost conductive pattern, a first contact plug disposed on a first pad region of the lowermost conductive pattern, a buffer conductive pattern disposed on a second pad region positioned above the first pad region, and a second contact plug formed on the buffer conductive pattern.

Contact structure and manufacturing method thereof

In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.

Semiconductor device and method of manufacturing the same

Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.

Method for forming silicide contacts

Provided are methods of forming a contact plug of a semiconductor device. Methods of forming a contact plug of a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate on which a lower structure is formed, forming a contact hole in the interlayer insulating layer, the contact hole exposing the lower structure, and forming a W layer and then a WN layer to form a W/WN barrier layer in the contact hole. Methods may include Hremote plasma treating the W/WN barrier layer, forming a W-plug on the Hremote plasma treated W/WN barrier layer to fill the contact hole, and chemical mechanical polishing (CMP) the W-plug and then the W/WN barrier layer in order to expose the interlayer insulating layer.

Method forming contact plug for semiconductor device using H2 remote plasma treatment

A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and forming a bit-line selectively on the exposed sidewall of the lower portion of the pillar-shaped active region.

Methods of manufacturing semiconductor devices and semiconductor devices manufactured using such a method

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Seongnam-si, South Korea

Ho-Ki Lee