Samsung Electronics Co., Ltd.

University of Seoul Industry Cooperation Foundation

University of Seoul Foundation of Industry Academic Cooperation

Ho-jung Kim

Jai-kwang Shin

Hyun-sik Choi

U-in Chung

Sang-beom Kang

Chul-woo Park

In-kyeong Yoo

Hyun-Ho Choi

Ki-ha Hong

Chang-jung Kim

Hyung-su Jeong

Myoung-jae Lee

Jong-seob Kim

Sung-chul Lee

Jae-joon Oh

David Seo

In-jun Hwang

Hyuk-Soon Choi

Jae-kwang Shin

Young-soo Park

Sun-ae Seo

Seung-eon Ahn

Chul-Woo Park

Sang-Hun Jeon

Seong-ho Cho

Young-Pil Kim

Sang-Beom Kang

Jong-wan Kim

Joong-ho Choi

Yeong-taek Lee

Hyun Ho Choi

Ki-chul Kim

I-hun Song

Sun-il Kim

Kyung-Eun Byun

Hyun-jong Chung

Jin-seong Heo

Kee-won Kim

Kwang-seok Kim

Chul Woo Park

Seong-jun Park

Hyun-Jae Song

Young-Sun Song

Hyun-su Jeong

A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

Logic devices, digital filters and video codecs including logic devices, and methods of controlling logic devices

According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

Graphene device and method of manufacturing the same

A power management chip and a power management device including the power management chip. The power management chip includes at least one power switch and a driver unit for generating a driving signal for driving the at least one power switch, the driver unit including one or more circuit units formed on a same substrate as the at least one power switch.

Power management chips and power management devices including the same

Field effect semiconductor devices and methods of manufacturing the same are provided, the field effect semiconductor devices include a second semiconductor layer on a first surface of a first semiconductor layer, a first and a second third semiconductor layer respectively on two sides of the second semiconductor layer, a source and a drain respectively on the first and second third semiconductor layer, and a gate electrode on a second surface of the first semiconductor layer.

Field effect semiconductor devices and methods of manufacturing field effect semiconductor devices

Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

Nonvolatile memory transistor and device including the same

A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.

Memory devices including graphene switching devices

A magnetic random access memory (MRAM), and methods of manufacturing and operating the MRAM, include a switching element and a storage node connected to the switching element, and a magnetic node configured to simultaneously store two opposite bits.

Magnetic random access memory having increased on/off ratio and methods of manufacturing and operating the same

Provided are a storage medium, which has a security function, for storing media content and an output apparatus for outputting data stored in the storage medium. The storage medium includes a controller for converting at least one of a position of pins of a connector and a storage position of media content in a memory unit in order to control transmission of the media content in the memory unit to the output apparatus.

Data storage medium having security function and output apparatus therefor

A high side gate driver, a switching chip, and a power device, which respectively include a protection device, are provided. The high side gate driver includes a first terminal configured to receive a first low level driving power supply that is provided to turn off the high side normally-on switch; a first switching device connected to the first terminal; and a protection device connected in series between the first switching device and a gate of the high side normally-on switch, the protection device configured to absorb a majority of a voltage applied to a gate of the high side normally-on switch. The power device includes the high side gate driver. In addition, the switching chip includes a high side normally-on switch, an additional normally-on switch, and a low side normally-on switch, which have a same structure.

High side gate driver, switching chip, and power device

A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks connected to first connection lines and the second logic blocks connected to second connection lines. The connection block electrically connected to the first and second logic blocks via the first connection lines and the second connection lines, respectively. The connection block including connection cells configured to select one of multiple connection configurations between the first connection lines and the second connection lines based on a desired function.

Logic device and operating method thereof

Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.

Image sensors having variable voltage-current characteristics and methods of operating the same

A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator.

Power module including leakage current protection circuit

A microprocessor chip includes a plurality of processors; at least one first optical input/output unit configured to receive optical signals from an external device and transmit optical signals to the external device; and an optical system bus that is connected between the plurality of processors and the at least one first optical input/output unit.

Microprocessor chip, data center, and computing system

A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.

Logic device and method of operating the same

Growing community of inventors

Suwon-si, South Korea

Ho-jung Kim