Samsung Electronics Co., Ltd.

Ho-Geon Song

Dong-hyeon Jang

Jun-Young Ko

Heui-seog Kim

Ho-jin Lee

Se-Young Jeong

Jae-Yong Park

Un-Byoung Kang

Tae-Je Cho

Teak-Hoon Lee

Min-Seung Yoon

Sung-jun Im

Ky-Hyun Jung

Sang-Sick Park

Won-keun Kim

Chang-Seong Jeon

Wha-su Sin

Sang-jun Kim

Jin-Woo Park

Dong-Woo Shin

Sun-Won Kang

Seung-Duk Baek

Mitsuo Umemoto

Kwang-Yong Lee

Seong-Chan Han

Hyo-Jae Bang

Sang-wook Park

Seok-hyun Lee

Dong-chun Lee

Jung-Seok Ahn

Jae-hyun Phee

Kwang-Su Yu

Kyoung-Soo Kim

Gun-Ho Chang

Geun-Woo Kim

Hwang-Bok Ryu

Man-Hee Han

A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad.

Semiconductor chip and semiconductor package including the same

In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

Method of molding semiconductor package

A method of fabricating a semiconductor device includes preparing a semiconductor substrate having a circuit unit on an upper surface thereof, a metal pad electrically connected to the circuit unit, and a passivation layer that covers the circuit unit and exposes the metal pad, forming a first re-wiring layer that is electrically connected to the metal pad and is formed by a printing method to extend from the metal pad on the passivation layer and forming a second re-wiring layer on the first re-wiring layer using the first re-wiring layer as a seed by using an electro-plating process.

Method of fabricating semiconductor device

Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings.

Double-sided adhesive tape, semiconductor packages, and methods of fabricating the same

A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed.

Method of manufacturing a flip chip package and apparatus to attach a semiconductor chip used in the method

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Method of manufacturing chip-stacked semiconductor package

A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

Stacked chips in a semiconductor package

A semiconductor apparatus having a through electrode, a semiconductor package, and a method of manufacturing the semiconductor package are provided. The method of includes preparing a substrate including a buried via, the buried via having a first surface at a first end, and the buried via extending from a first substrate surface of the substrate into the substrate; planarizing a second substrate surface of the substrate opposite the first substrate surface to form a through via by exposing a second via surface at a second end of the buried via opposite the first end; forming a conductive capping layer on the exposed second via surface of the through via; and recessing the second substrate surface so that at least a first portion of the through via extends beyond the second substrate surface.

Semiconductor apparatus, method of manufacturing the same, and method of manufacturing semiconductor package

A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.

Method of fabricating stacked chips in a semiconductor package

Provided is a lead frame that may include a frame, a lead structure, and a dam bar. The frame may include a plurality of openings configured to receive semiconductor chips. The lead structure may be in the openings. The lead structure may also include inner leads and outer leads. The inner leads may be configured to electrically connect to the semiconductor chips and the outer leads may extend from the inner leads. In example embodiments, the lead structure may extend in a first direction. The dam bar may be arranged between the inner leads and the outer leads. In accordance with example embodiments, the dam bar may extend along a second direction which is substantially perpendicular to the first direction. In example embodiments, the dam bar may have a first strength-reinforcing portion extending along the second direction. Also provided is a semiconductor package having the lead frame.

Lead frame and semiconductor package having the same

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Suwon-si, South Korea

Ho-Geon Song