Rca Inc.

US Government As Represented by the Secretary of the Army

Ho-Chung Huang

Franco N Sechi

Mahesh Kumar

Daniel D Mawhinney

Walter F Reichert

Raymond J Menna

Saligrama N Subbarao

Ralph J Matarese

A high power high frequency field effect transistor is achieved with a vertical structure of gallium arsenide including a semi-insulating substrate, a conductive layer over the substrate, a narrow-central post having small metal gate electrodes on each side, metal drain electrodes on the conductive layer spaced from the central post and a metal source electrode supported on the central post. A deep channel around the post separates the metal drains, gates and source. Increased power is obtained from a cellular unit including two parallel source stripes, four gates and three drains. The drains are connected together by the conductive layer and a drain pad at one end, and the gates are connected at the other end by a gate pad on an outer region of the substrate. The gate connections to the pad are isolated from the conductive layer by a bridge over a space etched in the lower layer. A method for fabrication of this structure is also provided.

Vertical MESFET with air spaced gate electrode

A predistortion circuit for a radio frequency power amplifier which has gain and phase shift characteristics that are non-linear as a function of power level of an RF input signal. The circuit includes a dual gate FET, with a drain coupled to the power amplifier. A modulated RF input signal is applied to an inductive matching network which is coupled to the signal gate of the FET. A modulating envelope detected version of the input signal is applied to a video amplifier which is coupled to the FET control gate. The signal applied to the control gate varies the gain of the FET as a function of input signal to compensate for the non-linear gain characteristic of the power amplifier and in conjunction with the matching network causes a phase change of the signal through the predistortion circuit to compensate for the non-linear phase characteristic of the power amplifier.

Predistortion circuit for a power amplifier

A monolithic voltage controlled oscillator is fabricated on a single semiconductor body. The oscillator includes an FET and a varactor diode interconnected such that a voltage applied across the varactor modulates the oscillating frequency of the FET output.

Monolithic voltage controlled oscillator

A 0.degree. and 180.degree. hybrid power divider/combiner includes a first quadrature hybrid and two other quadrature hybrids arranged in tandem with one output port of the first hybrid connected to an input port of the tandem arrangement and the other output port thereof connected to a delay of electrical length equal to that of the tandem arrangement. When an input signal is applied to one input port of the first hybrid with the other port terminated, two signals of reduced amplitude which are either in phase or of opposed phase (dependent on which input port receives the input signal) are produced at the output of the tandem arrangement and delay.

Hybrid power divider/combiner circuit

A circuit pattern is formed on a front side surface of a semiconductor wafer and an apertured photoresist pattern is formed over the circuit pattern. Via holes are then formed by laser irradiating the wafer at sites corresponding to the photoresist apertures. The back side surface of the wafer is next metallized and this surface is adhered to a plating block by means of an adhesive layer. Electrical connection between the substrate and plating block is then made, the via holes are electroplated, and the substrate is separated from the plating block and adhesive layer.

Method for fabricating via holes in a semiconductor wafer

A method of designing a linear rf amplifier comprising an output load impedance and an active device including the steps of (a) applying DC bias to the device, (b) applying two different frequency signals of an amplitude C, and (c) changing the value of the load impedance and recording the impedance value and associated C/I ratio for each impedance value (C/I being the ratio of amplitude C and amplitude I--the amplitude of an intermodulation product frequency). The last step (c) is repeated for a plurality of output levels. The above is repeated for a plurality of input power levels. The next step is selecting from the recorded information the impedance values corresponding to the maximum C/I ratio and recording the impedance values and corresponding C/I ratios, input power levels and output power levels. Then, choosing a desired C/I ratio from those recorded in the previous step and selecting the impedance value corresponding to the maximum output power level.

Design method for linear amplifier

A semiconductor device includes a body of semiconductor material on which are formed a plurality of spaced semiconductor elements. Each of the semiconductor elements includes a plurality of contacts, some of which are separated from each other by recesses in the semiconductor body. A metal grid is on the semiconductor body and surrounds each of the semiconductor elements. At least one of the contacts of each element extends to and is connected to the grid. The grid serves to electrically connect the contacts of all the semiconductor elements to permit the electrical plating of the contacts. Those contacts of each semiconductor element which are not directly connected to the grid are electrically connected thereto through the semiconductor body and an adjacent contact which is directly connected to the grid.

Semiconductor device having grid for plating contacts

A method for fabricating a semiconductor device having a pair of laterally spaced metal contacts adjacent a source and a drain, respectively, both contacts being located on a principal surface of a monocrystalline semiconductor, the contacts being separated by a groove therebetween. An edge of each of the contacts is extended in a cantilevered fashion over the groove, and a channel for the semiconductor is located under the groove. First and second laterally spaced Schottky-barrier gates are located in the groove adjacent the channel. In the method, the two Schottky-barrier gates are formed by deposition of a wide single gate onto a principal flat surface of the groove. The wide single gate is divided lengthwise into two separate Schottky-barrier gate conducting means by removing a portion of the gate through a photolithographically defined slot in a layer of a resistant means such as a photoresist or an ion-beam resist.

Growing community of inventors

Princeton Junction, NJ, United States of America

Ho-Chung Huang