Samsung Electronics Co., Ltd.

Ho-cheol Lee

Hyun-Soon Jang

Si-Yeol Lee

Churoo Park

Seung-Hun Lee

Yun-Ho Choi

Tae-jin Kim

Myung-Ho Kim

Chull-Soo Kim

Young-min Cheong

Jong-Jin Lee

Seung-hun Lee

Chul-soo Kim

Sang-Joon Hwang

Kyung-Woo Nam

Woo-Seop Jeong

Dong-seob Jang

Cheol-sung Yeon

Gyu-chan Jun

Jye-Sye Yeon

An optical reading and writing system including a base; an optical disk rotatably mounted on the base; an optical pickup including an objective lens, focusing a light beam to form a light spot on a recording surface of the optical disk; an actuator arm mounted on the base such that the actuator arm can pivot in the radial direction of the optical disk by a voice coil motor; a load beam supported by the actuator arm, and capable of moving slightly up and down and in the radial direction of the optical disk by an external force; a flexure attached to the load beam, supporting a slider to enable the slider to contact the recording surface; and a driving unit mounted on free ends of the actuator arm and the load beam, providing a driving force in the radial direction to the free end of the load beam.

Optical reading and writing system

A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

Integrated circuit memory devices having selectable column addressing and methods of operating same

Multi-bank dynamic random access memory devices having all bank precharge capability

Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation

A semiconductor memory device having reduced sensing noise and sensing current by reducing the number of cells activated by a word line is provided. The semiconductor memory device includes a memory cell array, which is segmented into a plurality of memory cell groups in a column direction, and a plurality of sub-word line drivers for selectively activating the sub-word line of a corresponding memory cell group in response to a group selection signal. The semiconductor memory device prevents sensing operation from occurring in a memory cell group which is not selected, while sensing operation is performed in a memory cell group which is selected by the group selection signal.

Semiconductor memory device with reduced sensing noise and sensing current

An integrated circuit device such as an integrated circuit memory device, includes a first fuse group such as a first laser fuse group including a plurality of first laser fuses each having a first narrow end, a second opposite end which is wider and a bent central portion. Pitches of the first end of the plurality of first laser fuses are narrow and pitches of the second end are wide. The plurality of first laser fuses are adjacent one another. A second fuse group such as a second laser fuse group includes a plurality of second laser fuses each having a first wide end, a second opposite end which is narrower, and a bent central portion. Pitches of the first end of the plurality of second laser fuses are wide and pitches of the second end are narrow. The second plurality of laser fuses are adjacent one another. The first ends of the laser fuses in the first laser fuse group are adjacent the first ends of laser fuses in the second laser fuse group. The second ends of the laser fuses in the first laser fuse group are adjacent the second ends of the laser fuses in the second laser fuse group. The central portions of the outer laser fuses of the first and second laser fuse groups are not bent, but straight. Accordingly, when a specific laser fuse is blown, neighboring laser fuses need not be damaged, and the density of the laser fuse area may be increased.

Layout arrangements of fuse boxes for integrated circuit devices, including bent and straight fuses

Graphics memory devices include an output register having an input electrically coupled to an output signal line (DO) and first and second data output buffers responsive to first and second clock signals (CLK1, CLK2), respectively. The first data output buffer has an input electrically coupled to the output signal line (DO) and the second data output buffer has an input electrically coupled to an output of the output register. These memory devices also include at least one memory cell array and a read data driver that has an input electrically coupled to the memory cell array by an input/output signal line (I/O) and an output electrically coupled to the output signal line (DO). To provide improved performance for graphics processing applications, a clock signal generator is provided that generates the first and second clock signals at different frequencies and/or different phases relative to each other. The second clock signal is preferably generated at a higher frequency than the first clock signal so that data (e.g., screen refresh data) provided by the read data driver to the output register can be serially transmitted from the second data output buffer at a high data rate. This data can also be transmitted in parallel with data being transmitted from the first data output buffer. In particular, the first data output buffer generates data at its output (first port) in response to a rising or falling edge of the first clock signal, but the second data output buffer generates data at its output (second port) in response to rising and falling edges of the second clock signal. Thus, even if the first and second clock signals have the same frequency, the rate of data being transmitted by the second data output buffer can be higher than the rate of data being transmitted by the first data output buffer.

Synchronous memory devices having dual port capability for graphics and

A redundancy fuse box of a semiconductor memory device which minimizes address line loading by organizing fuse cells into fuse cell groups sharing the same sub-address line. The address signal therefore has to traverse across a shorter distance along the semiconductor device, which contributes to a reduction in cell line loading. The redundancy fuse box includes a plurality of fuse cells, each having a transistor and fuse, to which an address signal of a memory cell is applied. The respective fuse boxes are constructed as one fuse box by being laid out in the same place. The fuse box includes a plurality of fuse cells which receive the same address signal along a common sub-address line and is wired so that outputs of the fuse cells which received the same address signal contribute to different redundancy enable signals.

Redundancy fuse box and method for arranging the same

Circuit in a semiconductor memory for programming operation modes of the

Synchronous dram having a plurality of latency modes

There is provided a semiconductor memory device which does not require an additional input pad to apply a signal for discriminating between a normal cell and a redundant cell. The semicodnuctor memory device has (claim 1). Therefore, the normal cell array or the redundant cell array is sequentially selected and tested by using the same input pad to which the bank select bit is input, without an additional pad.

Semiconductor memory device

A word line voltage boosting circuit varies a word line output voltage according to variation of the number of the word lines to be activated. A boosting circuit boosts a word line voltage which has been precharged to a first level voltage to a second level voltage in response to an activation signal. A voltage adding circuit further boosts the word line voltage to a third voltage level by adding a predetermined voltage to the second level voltage if the number of the word lines to be activated increases. A driving circuit includes a bootstrap circuit for stably providing the boosted word line voltage to an output line.

Word line voltage boosting circuit and method thereof

A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.

Semiconductor memory device having high speed parallel transmission line

System for selecting one of a plurality of memory banks for use in an

A data input/output sensing circuit of a semiconductor memory device including a plurality of memory cells, the circuit comprises: input/output lines of the memory cell; data input/output terminals connected to outside of the memory cells; a single data input/output line connected between the input/output lines and the data input/output terminals; a sensing unit for sensing whether or not effective data is provided in the data input/output lines to thereby generate a sensing signal; an output driving unit for transmitting data of the data input/output lines to the data input/output terminals in response to the sensing signal; and a writing driving unit for inputting data of the data input/output terminals in response to the sensing signal.

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Seoul, South Korea

Ho-cheol Lee