Samsung Electronics Co., Ltd.

Ho-Bin Song

Jae Hyun Park

Tae-Pyeong Kim

Cheon-Oh Lee

Jun Han Bae

Byeong Gyu Park

Jaehyun Park

Sung-Jun Kim

Junhan Bae

Han-Kyul Lim

Gyeongseok Song

Hajung Park

Kyung-seok Song

Byoung-joo Yoo

Jung-Myung Choi

Yun Geun Nam

Gyeong Seok Song

Kyeong-Joon Ko

Provided is an analog front-end receiver including: a first equalizer including a first block switch configured to receive a first differential signal through a first node, and configured to block the first differential signal in a first operation mode; a second equalizer including a second block switch configured to receive a second differential signal through a second node, and configured to block the second differential signal in the first operation mode; a terminating resistor provided between the first node and the second node, and configured to receive the first differential signal via the first node, and receive the second differential signal via the second node; and a low pass filter configured to receive a third differential signal converted by the terminating resistor from the first differential signal, and configured to receive a fourth differential signal converted by the terminating resistor from the second differential signal.

Analog front-end receiver and electronic device including the same

Disclosed is an integrated circuit including a first bias current generating circuit. The first bias current generating circuit includes a first amplifier receiving a reference voltage and a first voltage and amplifying a difference between them to output a first output voltage, a first bias current generator receiving the first output voltage and outputting a first bias current in response to the first output voltage, a variable resistor receiving the first bias current and outputting the first voltage in response to the first bias current and a calibration code, a second bias current generator receiving the first output voltage and outputting a second bias current to a peripheral circuit in response to the first output voltage, and a third bias current generator receiving the first output voltage and outputting a third bias current to an external device through a first pad in response to the first output voltage.

Integrated circuit using bias current, bias current generating device, and operating method for the same

An analog front-end receiver including a termination resistor configured to receive first and second differential signals from different data lines, the second differential signal being differential with respect to the first differential signal, an active equalizer configured to receive a first input differential signal through a first input node and a second input differential signal through a second input node, the first and second input differential signals both having an input common mode voltage, the first and second input differential signals being based on the first and second differential signal, respectively, and output first and output differential signals to first and second output nodes, respectfully, the second output differential signal being differential with respect to the first output differential signal, and an input common mode voltage generator configured to adjust the input common mode voltage to be equal to an output common mode voltage of the first output differential signal.

Analog front-end receiver and electronic device including the same receiver

A clock data recovery circuit configured to generate frequency step that is uniform regardless of operational conditions of the clock data recovery circuit.

Clock data recovery circuit and receiver including the same

A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.

Digital duty cycle correction circuit

Provided is a semiconductor device for compensating for an internal skew without training with an external device. The semiconductor device includes a signal generating unit configured to generate and output a reference signal, a first receiving unit configured to receive the reference signal and output a first output signal, a second receiving unit configured to receive the reference signal and output a second output signal, a delay unit configured to delay the first output signal by a certain time and output a delayed signal, a sampling unit configured to sample the second output signal based on the delayed signal and output sampling data, and a skew controlling unit configured to control the delaying unit based on the sampling data.

Semiconductor device compensating for internal skew and operating method thereof

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Daejeon, South Korea

Ho-Bin Song