Renesas Electronics Corporation

Hitachi, Ltd.

Renesas Technology Corp.

Other

Hizuru Yamaguchi

Junji Noguchi

Nobuo Owada

Tatsuyuki Saito

Takayuki Oshima

Naofumi Ohashi

Tsuyoshi Tamaru

Noriko Miura

Kensuke Ishikawa

Kiyomi Katsuyama

Tomio Iwasaki

Yoshio Homma

Seiichi Kondo

Toshinori Imai

Kenji Hinode

Kazumasa Yanagisawa

Hideo Aoki

Eiichi Murakami

Kazuyuki Tsunokuni

Kan Takeuchi

Takako Funakoshi

Kousuke Okuyama

Tomio Iwaskai

Kenichi Takeda

Noriyuki Sakuma

Jun Sugiura

Atsumi Aoki

Sekiko Ozono

Atsumi Yasuda

Tadashi Kamata

Mitsuharu Honda

The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Semiconductor device and manufacturing method thereof

A semiconductor IC device includes a buried interconnection in interconnection layers over a semiconductor substrate, in which electrical connection of interconnections are provided over and under an interconnection layer of an embedded interconnection from among the interconnection layers such that a first connecting conductor portion within a connecting hole extending from an upper interconnection toward the interconnection layer of a predetermined buried interconnection and a second connecting conductor portion within the connecting hole extending from a lower interconnection toward the interconnection layer of the predetermined buried interconnection are electrically connected via a connecting conductor portion for relay in the connecting groove of the interconnection layer of a predetermined buried interconnection. The connecting conductor portion for relay is sized so that the length of the connecting conductor portion for relay in an extending direction of the predetermined buried interconnection is longer than that of the connecting hole.

Semiconductor integrated circuit device and fabrication process thereof

In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Process for manufacturing semiconductor integrated circuit device

In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 &#x3bc;m and is smaller than about 1.44 &#x3bc;m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 &#x3bc;m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Method of manufacturing a semiconductor integrated circuit device

A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 &#x3bc;m and is smaller than about 1.44 &#x3bc;m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 &#x3bc;m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Semiconductor integrated circuit device

Growing community of inventors

Akisima, Japan

Hizuru Yamaguchi