Cadence Design Systems, Inc.

Hiu Ming Lam

Xiaobin Yuan

Mouna Safi-Harab

Jeremy Walker

Dimitri Loizos

Mohammad Ranjbar

The present embodiments relate generally to data communications, and more particularly to systems including high-speed serializer-deserializer circuits having TCOILs. One or more embodiments are directed to a four-terminal TCOIL structure that consumes the same amount of area on a chip as a traditional three-terminal structure, while providing more bandwidth and less reflection and group delay variation.

Compact four-terminal TCOIL

According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to conventional approaches.

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San Jose, CA, United States of America

Hiu Ming Lam