Micrel, Incorporated

Bcd Semiconductor Manufacturing Limited

Hiu Fung Ip

Ellick Ma

Martin J Alter

Yan Yu

Martin E Garnett

Robert W Rumsey

Michael Joseph Mottola

Arthur Lam

Helmuth R Litfin

Lawrence R Sample

Ji-Wei Sun

Ping Huang

Marty E Garnett

Marshall D Stone

Ren Chong

Ellick L Ma

A bimetal layer manufacturing method includes the procedure of: forming a first dielectric layer on the surface of a semiconductor substrate which has a first metal layer (conductive layer) of a selected pattern formed thereon; forming a SOG layer on the surface of the first dielectric layer; forming a second dielectric layer; forming required via holes on the foregoing layers until reaching the first metal layer; forming a linear layer from a dielectrics material through PECVD; removing unnecessary linear layer from selected locations through an anisotropic plasma etching process; finally forming a second metal layer on a selected surface of the linear layer where MIM capacitors to be formed, and forming connection plugs in the via openings without generating via hole poison.

Bimetal layer manufacturing method

The present invention relates to an integrated circuit manufacturing method for producing a double-diffused metal-oxide-semiconductor (DMOS), which utilizes a removable spacer method with a self-aligned channel to manufacture an improved DMOS with a reduced parasitic capacitance, and a high-resistance DMOS for a high power application can thus be fabricated also. Via the present invention, a faster switch with more usable operating frequencies can be achieved.

Method of manufacturing improved double-diffused metal-oxide-semiconductor device with self-aligned channel

A test structure pattern includes a first comb, a second comb, and a serpentine line. The first comb includes a first set of tines of the same orientation. The second comb includes a second set of tines of the same orientation that are interdigitated with the first set of tines. The serpentine line runs between the interdigitated tines of the first metal comb and the second metal comb. The test structure pattern forms a first metal comb, a second metal comb, and a serpentine metal line on a die. Print quality and resolution is tested by checking for electrical continuity in the serpentine metal line and bridging between the serpentine metal line and one of the first metal comb and the second metal comb.

Electrical print resolution test die

Each die containing a resistive element which is to be trimmed has associated therewith a plurality of alignment targets. A cut mask having a trim pattern and an alignment key formed thereon is employed in a masking and etching step to trim the resistive element to a desired resistance. The number of links cut in the resistive element, and thus the final resistance thereof, depends on the particular positioning of the cut mask with respect to the die as determined by which of the alignment targets is aligned with the alignment key. For instance, aligning the alignment key with a first alignment target would result in cutting one link in the resistive element so as to achieve a first resistance value, while re-aligning the cut mask such that the alignment key aligns with another of the alignment targets would result in cutting two links in the resistive element so as to achieve a second resistance value. Since the trim of resistive elements may be adjusted to any one of many possible resistance values by simply changing the alignment of the cut mask with respect to the die, the need to have a separate cut mask for each of the possible trimmed resistance values is eliminated, thereby reducing costs.

Method of forming a resistor having a serpentine pattern through

A structure and method are disclosed which allow for a more efficient use of silicon in a wafer fabrication process. In accordance with the present invention, the layout of masks used in the fabrication of circuit dice is modified by re-configuring the operating protocol of the stepper such that the alignment keys and targets are formed in the two subfields lying in the upper-left and upper-right corners, respectively, of each field. Thus, the 200 .mu.m-wide portion of each field previously used for alignment (i.e., alignment scribe line 34 of FIG. 2) may now contain patterns used in the formation of circuit dice, thereby increasing the amount of usable surface area on the associated underlying wafer. The operating protocol is further modified such that scribe lines separating rows and columns of subfields are less than 100 .mu.m wide, thereby resulting in a further reduction in the unused or wasted portions of the silicon wafer, particularly in applications having a large number of small die formed on the wafer.

Mask structure having offset patterns for alignment

One embodiment of the invention includes multiple patterns on a single mask, where all the patterns on the single mask are used for forming a single product. In the preferred embodiment, each of four quadrants of a mask have a different process layer pattern, where each of the four patterns is associated with a different process layer for the same product. After exposure of the wafer using the mask, the mask is rotated 90.degree. for the next exposure step so that the mask pattern image for the next layer to be formed on the wafer will overlie the designated quadrant of the wafer which will contain the final product. Although, by using this technique, three-quarters of the wafer will be unusable, this partial waste of the wafer will be offset by the savings in mask costs with low volume production, in prototyping situations, and in product debugging. Using the above technique, conventional mask exposure machines may be used.

Mask having multiple patterns

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San Jose, CA, United States of America

Hiu Fung Ip