Fujitsu Corporation

Fujitsu Microelectronics Limited

Hitoshi Yamanaka

Takahisa Hiraide

Tatsumi Nakada

Daisuke Maruyama

Akihiko Ohwada

Masahiro Yanagida

Hideaki Konishi

Junko Kumagai

A storage circuit, an integrated circuit and a scanning method are provided. The storage circuit includes a first storage element, and a second storage element connected to an output of the first storage element. The storage circuit includes a first setting circuit that is configured to set data of a first logic value to the first storage element when a clear signal is applied, and a second setting circuit that is configured to set data of a second logic value to the second storage element and transmit the second logic value data to a different storage circuit when a second clock signal is in an off state and the clear signal is applied.

Storage circuit, integrated circuit, and scanning method

An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

Testing apparatus and testing method for an integrated circuit, and integrated circuit

In processors having multiple cores, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block, which makes it possible to perform LSI tests more efficiently. A processor includes a plurality of logic block circuits, which include at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits. The processor further includes, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.

Multicore processor test method

Growing community of inventors

Kawasaki, Japan

Hitoshi Yamanaka